5 - 10 years
1 - 2 Lacs
Posted:2 days ago|
Platform:
Work from Office
Full Time
Exp 5-10 yrs
NP: Immediate to 45 days
Location : Pune/Bangalore
Skills : system Verilog, PCIe, Ethernet, verification
JD:
You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals.
You will also assist with developing test-plans, debugging failures and analyzing coverage information.
Must have excellent knowledge of computer architecture and design verification fundamentals
Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
Must have experience in developing complex test bench in System Verilog using OVM/UVM methodology
Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol
Experience in Low Power Simulation/UPF setup, debug low power simulation failures.
Exposure to scripting languages like Perl, Unix shell or similar languages
Good to have some experience with assembly language programming required
Excellent written and oral communication skills necessary.
Sincera Consulting India
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