25 Cxl Jobs

KEY RESPONSIBILITIES: Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure Handle regression testing and contribute to verification infrastructure development Develop both directed and random verification tests Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issues Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirement Collaborate with design, software and architecture teams to verify design under test PREFERRED EXPERIENCE: Proficient in IP-level FPGA and ASIC verification Knowledge of PCIe, CXL or other IO protocol is preferred Proficient in Verilog/SystemVerilog, and scripting languages such as Perl or Python Hands-on experience with SystemVerilog and UVM is mandatory Experience in developing UVM-based verification testbenches, processes, and flows Solid understanding of design flow, verification methodology, and general computational logic design and verification THE ROLE: As aSilicon Design Engineer,you will work withformal experts and designers to verify formal properties and drive convergence. ACADEMIC CREDENTIALS: BachelorsorMastersdegree in computer engineering/Electrical Engineeringwith 4+Yrs of exp

You are a skilled professional with expertise in design and validation, ready to join a dynamic and innovative team. Your background includes developing and validating FPGA-based solutions, with solid knowledge of PCIe, CXL, USB, and other protocols. You are enthusiastic about tackling daily technical challenges and possess qualities such as self-motivation, proactivity, responsiveness, persistence, and outstanding problem-solving skills. Your key responsibilities will involve developing and implementing comprehensive validation plans for various interface solutions, ensuring compliance with industry standards. You will design FPGA-based solutions to support Hardware Assisted Verification (HAV) and conduct thorough testing and validation to identify and resolve issues. Collaboration with design teams, documentation of validation processes, and clear reporting to stakeholders will be essential. Additionally, you will work closely with cross-functional teams to ensure seamless project execution and stay updated on industry trends and advancements in validation methodologies and tools. To qualify for this role, you should hold a Bachelors or Masters degree in Electronics, Electrical, or Computer Engineering (or a related field) with a minimum of 8 years of design and validation experience. Your expertise should include extensive knowledge of FPGA-based design and validation methodologies, a strong understanding of high-speed protocols like PCIe, CXL, and USB, and proficiency in programming languages such as C/C++, SystemVerilog, Verilog, Perl, Python, and TCL. Experience with emulation or prototyping platforms like ZeBu or HAPS would be advantageous. Your problem-solving skills, attention to detail, communication, and collaboration abilities are crucial for effective teamwork and project success.,

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, particularly using industry-standard protocols and methodologies, this role offers a challenging opportunity for individuals well-versed in System Verilog, Verilog, and Object-Oriented Programming. As a successful candidate, you will have demonstrated your ability to lead the development of reusable Verification environments on at least 2 projects using VMM, OVM, or UVM methodologies. Your expertise should extend to protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development and updates, and collaborating with Architects and methodology experts to address issues and drive architectural and methodological perspectives. If you are a proactive and reliable professional with a passion for Verification, we invite you to share your updated CV with us at taufiq@synopsys.com. Feel free to refer anyone who may be interested in this exciting opportunity as well. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Join us in shaping the future of technology.,

SoC NoC Verification Engineer - Lead Experience: 10+ Years Work location: Bangalore Job Description: SoC NoC Verification Lead with 10+ years of experience, the role typically expands to include leadership, strategic planning, and advanced debugging. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities: Lead verification projects for complex SoC and NoC architectures. Develop advanced verification methodologies using SystemVerilog/UVM. Guide teams in debugging and resolving intricate design issues. Optimize performance, power, and coverage metrics. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Manage testbench architecture and automation frameworks Role & responsibilities Preferred candidate profile

As a Verification Engineer at Google, you will play a crucial role in ensuring the functionality and performance of Google's custom silicon solutions. You will be responsible for verifying digital systems, including infrastructure IP, interconnects, caches, memory management, and system services. Your expertise will be instrumental in shaping the next generation of hardware experiences, delivering unmatched performance, efficiency, and integration. Your responsibilities will include planning and executing the verification of configurable Infrastructure IPs, interconnects, and memory subsystems. You will develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Additionally, you will create cross-language tools and scalable verification methodologies to ensure comprehensive testing coverage. To excel in this role, you should have a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. You should possess experience in verifying digital systems using standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems. Proficiency in Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, and Python is required. Experience in creating and using verification components and environments in standard verification methodology, scripting languages, and software development frameworks is essential. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering or Computer Science, along with 3 years of experience in areas such as Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers. Experience with building verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is advantageous. Knowledge of Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL), performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation is also beneficial. Join our team at Google and be part of the innovation that drives the future of direct-to-consumer products. Your contributions will have a global impact, shaping products loved by millions worldwide. Embrace the opportunity to work on the verification of Google's System on a Chip (SOC) offerings, collaborating with hardware architects and design engineers to deliver cutting-edge hardware experiences. Your role will involve developing performance Virtual IP address (VIPs) for supported protocols, deploying verification stacks across diverse IPs, and building generalized system topology abstractions. Together, we will develop methodologies and tools to tackle complex challenges and advance technology for the betterment of society.,

As a Technical Lead or Senior Developer, you will be responsible for developing embedded software for various processors. Your expertise in developing drivers for different hardware blocks such as SSD (NVMe/SATA/SCSI), NVMeOF (NVMe over RDMA or TCP/IP), RDMA-NIC, iSCSI, NVMeOF, PCIe, RAID, and Ethernet will be crucial. Additionally, you should have a deep understanding of Linux kernel internals and experience in development based on open-source software. Exposure to different hardware/software development and debugging tools like Trace 32, JTAG, and Lacroy-PCIe Analyzer is expected. Your responsibilities will include developing high and low-level designs, drivers, and firmware for different hardware blocks. You will need to adopt operating systems and embedded software for various processor architectures, develop software based on pre-silicon development vehicles, and perform software bring-up using pre-silicon vehicles and silicon-based platforms. Upstreaming of open-source code and developing software component-level tests for integration into CI/CD systems are also part of your role. Additionally, you will be expected to debug issues using standard hardware/software-based debuggers and diagnosing equipment like Trace 32, JTAG, and Lacroy-PCIe Analyzer. To excel in this role, you should possess excellent knowledge of Linux internals and various drivers. Strong familiarity with different standards protocols such as NVMe, NVMeOF, iSCSI, RAID, PCIe, RDMA-NIC, Ethernet, and CXL is essential. A good understanding of hardware architectures in relation to the aforementioned standards is also required. Expertise in the Software Development Life Cycle (SDLC) and advanced development & debug capabilities in Firmware BSP and device drivers are crucial. You should be adept at solving complex technical problems related to system boot, UEFI, and OS functionality and be able to code to standards while integrating with existing solutions using languages like C, C++, and Python. Strong low-level debugging skills enabling root cause analysis of firmware, hardware, and OS internals are expected. Additionally, a good understanding of various CPU architectures, preferably IA, ARM, and RISC V, and the Pre-Silicon Development environment will be beneficial. Qualifications for this role include a BTech/MTech in Computers, Electronics, or Electrical Engineering and around 5 to 8 years of experience in embedded software development across different architectures.,

Key Responsibilities: Develop and execute comprehensive verification plans for SoC and NoC systems Design and maintain test benches using SystemVerilog and UVM Perform functional, performance, and low-power verification Debug and resolve design/verification issues independently Work with high-speed protocols such as AXI, CHI, PCIe, Ethernet, CXL, and UCIe Ensure thorough coverage and compliance with design specifications Collaborate with cross-functional teams including RTL, DFT, and architecture Required Skills: 7+ years of hands-on experience in SoC/NoC verification Strong expertise in System Verilog, UVM, and scripting (Python/Perl/TCL) Experience with simulation tools like VCS, Questa, or Incisive Solid understanding of interconnect protocols: AXI, CHI, PCIe, Ethernet, etc. Familiarity with coverage analysis and debugging tools Strong analytical and problem-solving skills Preferred: Experience with CXL or UCIe protocols Exposure to formal verification or emulation tools is a plus

Job Description : We are looking for experienced DV Engineers with a strong background in ARM-based SoC and Subsystem Verification to join our team for exciting semiconductor projects. Key Responsibilities : Perform Design Verification of ARM-based SoC / SS level components Work on Cortex-A / Cortex-M series SoC Debug using CoreSight infrastructure (implementation or validation) Handle RTL / GLS regressions and perform deep simulation-level debugging Develop or maintain testbenches, checkers, and scoreboards in SystemVerilog/UVM Implement C/C++ modeling as needed for verification environments Technical Skills Required : Strong hands-on in SystemVerilog, UVM Experience with ARM protocols : AXI, AHB, APB, CHI, ACE Solid debugging in NoC, memory subsystems Proficiency in C/C++ Exposure to GLS (Zero delay, SDF, PA GLS) simulations is a plus Knowledge of memory protocols: LPDDR4, LPDDR5, DDR, HBM preferred Experience in PCIe, CXL, Ethernet protocols is a plus Scripting (Python, Perl) – good to have for automation and flow enhancements Desired Candidate Profile : 5+ years of experience in DV Must be proactive , with strong debugging & simulation skills Capable of working independently or as part of a dynamic team How to Apply : Email your CV to: Richa.smriti@orcapod.work , contact: +91 92349 19275

Qualcomm India Private Limited is a leading technology innovator that strives to push the boundaries of what is possible, enabling next-generation experiences and driving digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams will be essential to develop solutions and meet performance requirements. To be eligible for this position, you should have a Bachelor's/Master's/PhD degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with relevant work experience ranging from 4 to 6+ years. Join Qualcomm's design verification team and be involved in verifying high-speed mixed-signal IP designs for products targeted for 5G, AI/ML, compute, IoT, and automotive applications. Responsibilities will include defining test plans, developing testbenches using advanced verification methodologies, authoring assertions, developing test cases, and collaborating with various teams to ensure successful verification and integration. Qualified candidates should possess a Master's/Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with at least 12+ years of ASIC design verification experience. Knowledge of HVL methodologies like SystemVerilog/UVM and experience with ASIC simulation/formal tools are required. Preferred qualifications include experience with low power design verification, formal verification, gate-level simulation, knowledge of standard protocols, scripting languages like Python or Perl, and experience with mixed-signal IP design verification. Qualcomm is an equal opportunity employer that is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Additionally, Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. For more information about this role, please contact Qualcomm Careers.,

As a Developer/Senior Developer at Krutrim, you will be responsible for developing embedded software for different processors. You should have good knowledge in developing drivers for various hardware blocks such as PCIe, I2C, USB, UART, Ethernet, and Crypto security. Understanding Linux kernel internals and working with open-source software is essential for this role. You will be involved in developing high and low-level designs, drivers, and firmware for different hardware blocks. Additionally, you will work on adopting operating systems and embedded software for various processor architectures. Your responsibilities will include developing software based on pre-silicon development vehicles, bringing up software using pre-silicon vehicles and silicon-based platforms, upstreaming open-source code, developing software component-level tests, and enabling them in a CI/CD system. You will also be debugging issues using standard hardware/software-based debuggers and diagnostic equipment. To excel in this role, you should possess excellent knowledge of Linux internals, different drivers, and standards like PCIe, Ethernet, and CXL. Expertise in the Software Development Life Cycle (SDLC), firmware BSP, device drivers, and strong technical problem-solving skills in areas like system boot, UEFI, and OS functionality are crucial. You should have software development skills in C, C++, and Python, along with strong low-level debugging capabilities. A successful candidate for this position should hold a BTech/MTech in Computers, Electronics, or Electrical Engineering and have around 5-12 years of experience in embedded software development across different architectures. Having a good understanding of different CPU architectures like IA, ARM, and RISC V, as well as the Pre-Silicon Development environment, will be advantageous in fulfilling the requirements of this role.,

Standards Support & Ecosystem Engagement Collaborate with Technology Lead to run experiments that contribute to PCI-SIG, CXL, and IEEE standards development. Support industry workshops, compliance events, and Plugfest by preparing demo setups, running tests, and capturing data. Track relevant activity across PCIe, CXL, and Ethernet ecosystems and share actionable insights with product and engineering teams. 2. Engineering Enablement Work closely with engineering teams to define technical requirements and contribute to feature development. Validate early software builds, report issues, and offer feedback on usability, performance, and feature completeness. Develop and maintain Python-based automation scripts to streamline testing and validation processes. 3. Sales Enablement & Content Development Create technical content including datasheets, application notes, methods of implementation (MOIs), and web updates. Support webinars, product launches, and technical campaigns that articulate the value of Tektronix s PCIe/CXL and Ethernet offerings. Collaborate with marketing and product management to ensure messaging aligns with customer use cases and industry trends. 4. Pre-Sales Technical Support Deliver product demos, technical presentations, and training sessions to field teams and customers. Assist with customer evaluations, proof-of-concepts, and proposal development for PCIe/CXL and Ethernet solutions. Provide technical expertise to differentiate Tektronix in competitive engagements. 5. Post-Sales Customer Support Troubleshoot and resolve customer issues, managing bugs and actionable requests (ARs) with R&D teams. Maintain close engagement with key customers to ensure successful adoption and ongoing satisfaction. Provide feedback loops from the field to guide product improvements Who You Are A hands-on engineer with strong technical acumen in high-speed serial technologies such as PCIe, Ethernet and CXL. A proactive collaborator who thrives in cross-functional environments and is comfortable working directly with customers, engineering, sales, and standards bodies. A detail-oriented problem solver who enjoys translating technical complexity into customer-centric solutions. Qualifications Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or related field. 3+ years of experience in applications engineering, validation, or customer support in the test & measurement or semiconductor industry. Solid understanding of PCIe Gen5/Gen6, CXL, and Ethernet technologies (e.g., 100G/400G), including deep understanding of jitter, eye diagrams, and high speed signal integrity. Hands-on experience with lab equipment such as high-bandwidth oscilloscopes, BERTs, AWGs, and automation tools. Experience with Python for instrument automation, test scripting, or workflow enhancement Strong communication and presentation skills; ability to convey technical concepts clearly. Willingness and ability to travel (25-30%) both domestically and internationally.

Role & responsibilities Please interested candidate send me cv : galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Industry: SEMICON Position Name SoC NoC Verification Engineer Job No : PROX-14080 Position type: Permanent Total Exp: 7+ years to 15y HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore Job Description Must have: SoC NoC Verification Engineer with 7+ years of experience This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities Develop and execute verification plans for SoC and NoC architectures. Write and maintain test benches using SystemVerilog/UVM. Perform functional, performance, and power verification. Debug and resolve design and verification issues. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Work closely with design and architecture teams to ensure compliance with specifications. Client is looking for Network on chip , just look for the NoC verification AMD (Dont Share AMD Profiles) Preferred candidate profile

Role: SoC NoC Verification Lead Location: Bangalore Job Type: Full Time Work mode: Onsite - 5 days WFO 10+ years of experience, the role typically expands to include leadership, strategic planning, and advanced debugging. This role involves developing test plans, writing verification code, debugging issues, and collaborating with design teams to validate complex interconnect systems. Key Responsibilities: Lead verification projects for complex SoC and NoC architectures. Develop advanced verification methodologies using System Verilog/UVM. Good in verifying the communication between the CPU subsystem and the NoC (instruction/data/caches) not just general NoC trafficor peripheral interfaces. Working with cache, MMU, interrupt systems is also important. Cache coherency protocol testing Guide teams in debugging and resolving intricate design issues. Optimize performance, power, and coverage metrics. Work with high-speed interconnect protocols (AXI, CHI, PCIe, Ethernet, CXL, UCIe). Manage test bench architecture and automation frameworks.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: SoC Network on Chip Verification Engineer Location: Bangalore Work Type: Onsite Job Type: Full time Job Description: This role involves developing test plans, writing verification code, debugging issues, and collaborating closely with design teams to validate complex interconnect systems. Key Responsibilities: Lead verification projects for complex SoC and NoC architectures (for senior role). Develop advanced verification methodologies using SystemVerilog/UVM. Guide teams in debugging and resolving intricate design issues. Optimize performance, power, and coverage metrics. Work with high-speed interconnect protocols: AXI, CHI, PCIe, Ethernet, CXL, UCIe. Manage testbench architecture and automation frameworks. Note : profiles with solid experience in SoC + NoC verification and exposure to the above protocols. TekWissen Group is an equal opportunity employer supporting workforce diversity.

Develop emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers Write and maintain software components using C/C++ for emulation frameworks Create synthesizable RTL using Verilog for emulation model development Verify emulation models to ensure high performance, functionality, and reliability Collaborate with customers during deployment and debugging phases to ensure successful adoption Work with cross-functional teams to integrate emulation solutions across Synopsys products Maintain and update existing emulation platforms to comply with industry changes and customer needs The Impact You Will Have: Advance the development of standards-compliant and scalable emulation solutions Improve the performance and efficiency of semiconductor products through high-quality emulation Deliver superior customer support, enhancing the deployment experience and satisfaction Help Synopsys maintain a leadership position in silicon design and verification ecosystems Enable faster time-to-market for cutting-edge chips by providing robust emulation infrastructure Contribute to the adoption of next-gen interfaces and system-level design methodologies What You'll Need: 5+ years of relevant experience in semiconductor or hardware design domains Deep knowledge of PCIe, CXL, and UCIe protocol standards and usage Proficiency in C/C++ with strong object-oriented design understanding Good grasp of digital design concepts and proficiency in Verilog/SystemVerilog Experience with scripting languages such as Python, Perl, or TCL Familiarity with ARM architecture and functional verification (UVM) is a plus

Defining and developing ASIC RTL verification at both chip and block levels. Creating and executing verification plans for complex digital designs, particularly focusing on PCIe/CXL protocols. Collaborating with cross-functional teams to ensure seamless integration and functionality of designs. Utilizing advanced verification methodologies and tools to achieve high-quality results. Mentoring and guiding junior engineers, promoting best practices, and fostering a culture of continuous improvement. Communicating with internal and external stakeholders to align on project goals and deliverables. The Impact You Will Have: Enhancing the reliability and performance of Synopsys digital verification processes. Improving time-to-market for robust Synopsys Interface IP controller through efficient verification methodologies. Mentoring and nurturing a highly skilled verification team, elevating overall project quality. Influencing strategic decisions that shape the future of Synopsys capabilities. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous technological advancements. What You'll Need: Extensive experience in ASIC RTL verification. In-depth knowledge of PCIe, CXL , UCIe and similar IO protocols. Proficiency in advanced digital design verification tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 18+ years in relevant domain.

Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be go-to person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

Expertise in UVM and System Verilog Experience in verification IP modelling with knowledge of test case coding, scoreboard design, assertions, checkers & functional coverage. Involved & played a driving role in the development of reusable Verification environments for at least 2 verification projects using VMM/OVM/UVM methodologies. Protocol experience: Should have experience on UCIe / PCIe / CXL / Unipro / USB / MIPI / HDMI / Ethernet / DDR / LPDDR / HBM memory protocol Job responsibilities: Able to contribute to the development of the VIP Responsible & can be relied on for review sign-off of VIP development and updates from a technical perspective including methodology and protocol functional prospective. Liaison with Architects/methodology experts to achieve resolutions on issues or driving output from an architecture/methodology perspective. Locally should be to be go-to person on all technical aspects of VIP At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.Apply Now Save Relevant Jobs Senior Staff Product Engineer, R&D-7683Aschheim, GermanyEngineering Principal Analog Design EngineerMississauga, CanadaEngineering Verdi InternshipHsinchu, TaiwanInterns/Temp

The candidate will be part of the Synopsys CXL IP Design verification R&D team at Synopsys. You will own UVM based verification environment, which handles multiple features of IP, test plan creation, test case writing, random constraint creation, coverage closure, SVA and Release. As part of the work, you will closely work with lead and be part of a global team of experienced Engineers. Technical Expertise Needed: BS or MS degree in Computer Science, Electrical or Electronics Engineering, or Related Field with 8+ years of experience in the following areas: Own UVM based testbench environment and developed UVM testbench architecture, Testplan and SVA for an IP/SoC. Knowledge of one or more of protocols/standards: PCIe, CXL, UCIe, AMBA (AXI,APB,AHB) etc Good knowledge of System Verilog. Hands-on experience with coverage closure and writing SVA for IP/SOC. Good simulation debugging skills. Experience with Perforce or similar revision control environment. Experience with Python/TCL or any scripting knowledge is an added advantage. Job Responsibilities include - Understand Standard Specifications, create testplan for the product and create UVM based testbench architecture. Propose and enhance the UVM architecture with unique idea for verification. Be single point of contact with hands-on experience on all verification tasks - Testbench Creation - Testplan creation - Coverage closure - SVA - Release Perform peer review of testbench code for continuous quality. Own simulation debugs using DVE/Verdi, interact with Design Team and aid in debug and Verification closure. Periodically publish technical papers and/or file patents on the feature updates/innovation carried out. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. In addition, the candidate should have excellent oratory and written communication skills in English, should be a team player and possess good problem-solving skills and show high levels of initiative.

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a skilled Emulation R&D Engineer with over 8 years of experience and a strong academic background in Electronic & Communication or Computer Science Engineering Your expertise in C/C++, OOPS, and HDL languages like System Verilog and Verilog, along with your scripting skills in Perl or TCL, make you a valuable team member You possess knowledge of protocols such as ENET, HDMI, MIPI, AMBA, and UART, and have experience with UVM and Functional Verification You are a resourceful problem-solver, a team player, and have excellent communication skills, What Youll Be Doing: Designing and developing emulation models, Implementing and verifying digital designs using System Verilog and Verilog, Developing scripts in Perl, TCL, or other languages, Collaborating with cross-functional teams, Conducting protocol verification for various standards, Utilizing UVM for design validation, The Impact You Will Have: Enhancing emulation model efficiency, Contributing to high-performance silicon chips, Improving design reliability through verification, Streamlining workflows with automation, Ensuring protocol compliance, Driving technological advancements, What Youll Need: E / M Proficiency in C/C++ and OOPS, Knowledge of digital design and HDL languages, Experience with scripting languages, Familiarity with multiple protocols like ethernet, pcie, cxl, CSI, DSI, UFS AMBA, CHI and UVM, Who You Are: Effective communicator, Team player, Resourceful and detail-oriented, Innovative problem-solver, Adaptable learner, The Team Youll Be A Part Of: Join a dynamic team dedicated to developing and verifying advanced emulation models for high-performance silicon chips Collaborate with cross-functional teams to ensure seamless integration and adherence to industry standards, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits Your recruiter will provide more details about the salary range and benefits during the hiring process, Inclusion and Diversity: Synopsys considers all applicants for employment without regard to race, color, religion, sex, gender preference, national origin, age, disability, or status as a Covered Veteran in accordance with federal law,

Job Summary Key Responsibilities: Strong domain knowledge of storage technologies 10+ years of experience in storage related areas especially storage enclosure services 4+ years of experience working with SCSI, SAS, NVMe technologies Experience working with cross functional teams including product management, hardware engineering, manufacturing Strong knowledge of C, Python, RTOS concepts, multithreading, SMP Experience in designing and debugging high availability storage systems with redundant components Outstanding software debugging skills Key leadership skills 4+ years of experience in technical leadership role A track record of leading and mentoring a software team Ability to interact with customers to gather requirements, explain the design, troubleshoot issues in live environment Ability to understand the overall solution for the customer and translate this into a cost effective and reliable design Experience working with cross functional teams including product management, sales, hardware engineering, manufacturing teams to design high-performance, cost-effective solutions for storage platforms Ability to contribute and engage in authorized open source and external tech forums Other relevant and desirable Technical Skills (one or more of the below) Experience in RESTful API, Redfish, Swordfish, CXL Hands-on experience with one or more of Broadcom, Microchip SDK Other Requirements Physical Demands: Duties of this position are performed in a normal office environment. Duties may require extended periods of sitting and sustained visual concentration on a computer monitor or on numbers and other detailed data. Repetitive manual movements (e.g., data entry, using a computer mouse, using a calculator, etc.) are frequently required. Occasional travel may be required. Experience: Bachelors or Master degree in ECE, CS, IT or EE 10+ years of working experience and hands-on experience in one or more areas of the skills section Excellent verbal and written communication skills Strong interpersonal, multitasking and organizational skills Ability to work under pressure. Education: Bachelor degree or higher education in Engineering

Staff PCIe / CXL / D2D based memory expander Verification Location: Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/Bangalore A US based well-funded product-based startup looking for Highly talented Verification Engineers for the following roles. PCIe/CXL based memory expander - Verification Engineer: looking for experienced and talented professional for CXL based memory expander. Minimum Qualifications: BE/BTech in Electrical/Computer engineering with 6-8+ years of experience or Should have hands on experience in System Verilog, UVM and Object-Oriented Programming Proven track record in USB / PCIe / CXL / D2D IP verification both on FPGA and ASIC, with ability to bring up testbenches from scratch to defining test plan and sign-off for tape out. Integration and verification of complex System IP features. Work closely with RTL designers and SOC team to scope out integration and verification requirements. Good understanding of any memory protocol like DDR, ONFI, NAND, Flash SPI/QSPI. Proficiency in bus protocols AXI/AHB Proficiency in scripting languages like Perl, Python etc. Strong communication, collaboration, and interpersonal skills Strong analytical and problem-solving skills Preferred Qualifications: Experience in verification of PCIe/CXL based sub-system/SoC/IP. Knowledge of SoC with processor boot-flow. Knowledge of FPGA setup and running FPGA simulations. Experience in GLS is added advantage. Verification expertise in Physical Layer, Link Layer, and Transaction Layer of PCIe/CXL protocols. Experience with compliance at the physical and transaction layers for PCIe/CXL endpoints or root ports. Analysing performance metrics of CXL / PCIe / D2D System-level verification experience for PCIe / CXL / D2D Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Being part of DCS group, candidate will be working on PCIe, CXL based Switches, Re-timers and flash controllers for data-centers. Responsibilites: Create Micro-Architecture Specification. Work with team members to design RTL and provide support to verification. Work on constraint development for CDC, RDC and synthesis. Review Test plans from Verification team. Support Emulation and Firmware team in bringup. Qualifications/Requirements Qualifications/Requirements Minimum B.Tech/M.Tech in Electronics or related field. 10+ years of experience in RTL Design and timing aspects of IC design, with leadership capability. Key Skills: Expertise in VLSI logic design, understanding architecture and design planning. Expertise in synthesis/debugging, and timing closure. Knowledge of protocols like PCIe, CXL, AXI, AHB, I3C etc. Proficiency in Tcl and Perl scripting. Power planning and implementation techniques. Proficiency in CDC, RDC and constraint development. Excellent debugging, analytical, and leadership skills. Strong communication skills and interpersonal abilities.

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon RTL Design Engineer :- • Job Description o As a member of Design(RTL) team, you will be responsible for the microarchitecture and design of IPs/Controllers for SoC/SiP designs. o Perform architectural/design trade-offs for required product features, performance and system constraints. o Responsible for defining and documenting design specifications. o Develop and deliver a fully verified RTL to achieve the design targets and quality sign-off requirements. o Design and Implement logic functions that enable efficient test and debug. o Provide Debug support for design verification and post-silicon activities. • Skill and Experience Requirements: o Minimum 7 + years industry experience with Masters degree (preferred) or Bachelors degree in Electrical or Computer Engineering. o Hand-on experience with micro-architecture and RTL development (System Verilog) for x86/ARM CPU Processors or high-speed custom ASICs/Accelerators with focus on any one: Cache controller, IO interfaces (PCIe, CXL, Ethernet), UCIe, Memory controllers, Display, Video encoding/transcoding. o Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis and sign-off quality flows. o Self-starter with strong interpersonal and communication skills . o Excellent team player. .

Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Staff Design Verification Engineer Job Description In this role you will be responsible Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being launch ready for the end Product. Role And Responsibilities Partner with Architects and RTL Design team to grasp high-level system requirements and specifications. Formulate comprehensive test and coverage plans to match the Architecture and micro-architecture. Define and implement a verification methodology that supports scalability and portability across various environments spanning including post-silicon. Develop the verification environment and reusable bus functional models, stimulus, checkers, assertions, trackers, and coverage metrics. Create verification plans and develop testbenches tailored to assigned IP/Subsystem or functional domain. Execute verification plans, including tasks such as design bring-up, setting up the DV environment, running regressions for feature validation, and debugging test failures. Support post-Si bring-up and debug activities. Track and communicate progress in the DV process by using key metrics like bug tracking and coverage reports. Requirements Bachelors or Masters degree in Electrical or Computer Engineering/Science Strong Architecture domain knowledge in x86/ARM CPU, or Memory, Coherency, Virtualization or Performance areas. Must have strong expertise with SV/UVM methodology and/or C/C++ based verification with 7yrs+ hands-on experience in IP/sub-system and/or SoC level verification Hands on experience and expertise with industry standard verification tools for simulation and debug (Questa/VCS, Visualizer) Experience using random stimulus along with functional coverage and assertion based verification methodologies a must. Experience in one or more of the following areas along with functional verification - SV Assertions, Formal, Emulation. Preferred Qualifications: Experience in development of UVM based verification environments from scratch. Hands on expertise and protocol knowledge in any of: APB/AXI/CHI, JTAG/I3C/SPI, , DDR5/LPDDR5/HBM, PCIE/CXL/UCIE/Ethernet compliance testing