5.0 - 10.0 years

3 - 13 Lacs

Hyderabad, Telangana, India

On-site

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Should have worked hands-on Full chip DFT implementation, Scan, DRCs, ATPGgeneration & Simulations along with Pattern Porting/re-targeting and Coverage improvement Experience with Scan, Compression, ATPG and simulations withSynopsys EDAtools. Should have participated in successful tape-outs of SoC/ASIC chips at 3nm or below and achieved test targets. Descent understanding of front-end SoC/ASIC design and implementation including Synthesis and STA. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies & process Excellent problem solving and debugging skills. Proactive in nature Excellent Customer interaction, Communication and Team work skills

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DFT Engineer Shashwath Solution

6.0 - 8.0 years

6 - 8 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

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Roles and Responsibilities Develop RTL code using Verilog/VHDL Work with Mentor DfT tools and Cadence tools for design and verification Perform scan insertion, JTAG, ATPG DRC, and coverage analysis Debug simulations using timing and SDF Contribute to LBIST and Mixed Signal Radar IC-related projects (preferred) Investigate simulation failures and perform root cause analysis Collaborate with cross-functional teams; work independently and proactively Communicate effectively with both written and verbal communication

Posted 6 days ago

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CPU Power Delivery Engineer Intel

6.0 - 10.0 years

14 - 19 Lacs

Bengaluru

Hybrid

Job Details: You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for power delivery network design, IR Drop analysis and convergence of complex core design. Your Responsibilities Will Include But Not Limited To Responsible for power delivery network design including package/bump to device level delivery for over 5GHz Freq and low-power digital designs. Deep understanding of RV and IR Drop concepts. Load line definition Closely work with SD, Integration and Floor plan teams Qualifications: * You must possess a master's degree in electrical or Electronics Engineering with at least 6 or more years of experience in related field or a bachelor's degree with at least 8 years of experience. * With a deep Technical Expertise On - power delivery network IR and RV analysis, MIM spread with Tools: Redhawk, RHSC Additional preferred Skills being. * Technical Expertise in Static Timing Analysis is preferred. * Preferred Additional Skills Experience of handle complex core design, high-speed designs Timing signoff flows/tools experience both/either Synopsys/Cadence tools Very good knowledge on Timing tools, flows and methodology Ability to handle new feature feasibility studies SD flow knowledge would be plus Familiarity with Verilog/VHDL Tcl, Perl, Python scripting Strong verbal and written communication skills Shift: Shift 1 (India)

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DFT Engineer Shashwath Solution

6.0 - 8.0 years

25 - 40 Lacs

Bengaluru

Work from Office

The engineer should be well versed in Verilog/VHDL RTL coding, experienced in using Mentor DfT tools and Cadence tools. The engineer needs to have hands-on experience in scan insertion, JTAG, ATPG DRC and coverage analysis, Simulation debug with timing/SDF. Candidate with LBIST and Mixed Signal Radar IC experience is highly desirable Must be proactive, collaborative and detail-oriented capable of exercising independent judgment The engineer with experience on debug and root cause the problem in simulation failures Self-motivation, flexibility, with strong interpersonal skills. Effective communication skills, oral and written skills.

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