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ASIC RTL Designers Lint/CDC

2 - 6 years

0 Lacs

karnataka

Posted:4 days ago| Platform: Shine logo

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Skills Required

system design verilog sv vhdl cdc logic design asic synthesis sta timing closure soc axi ahb pcie ddr usb uart spi i2c synthesis timing analysis micro architecture design spyglass lint soc integration processor based system design apb system bus peripherals ethernet tcl python scripting

Work Mode

On-site

Job Type

Full Time

Job Description

The position requires 2-6 years of experience with micro architecture design and system design using Verilog, SV, or VHDL. You should also have experience in Spyglass Lint, CDC, SoC Integration, logic design with Verilog and SV, ASIC Synthesis, STA, timing closure, and working with any Processor based system. Familiarity with design using SoC, AXI/AHB/APB System bus, and peripherals such as Ethernet, PCIe, DDR, USB, UART, SPI, and I2C is essential. You will be responsible for synthesis, timing analysis using various industry standard tools, and should have proficiency in TCL and Python scripting. The ideal candidate for this role should have a notice period of immediate availability to 1 month. The position is based in BLR/Hyd locations.,

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ASIC RTL Designers Lint/CDC

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