8 Soc Integration Jobs

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL design Location : Bangalore Work Type: Onsite Job Type: Full time Job Description: 7+ years of RTL design experience with 4+ years focused on SoC integration Expert knowledge of industry-standard bus protocols (AXI, AHB, APB, etc.) Proven experience with large-scale integration challenges in complex SoCs Strong understanding of clock synchronization strategies and metastability management Deep knowledge of power management techniques and implementation Experience with integration-specific verification methodologies Proficiency in debugging complex system-level issues TekWissen Group is an equal opportunity employer supporting workforce diversity.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Experience in micro architecture and requirements/implementation for automotive designs (focused on functional safety) and their Safety Analysis work products like concept FMEDA, DFA, DFMEA, FTA, FMEDA, etc. including FuSa compliant IP development and third-party IP compliance/deliverables/DIA. Responsibilities shall include the following Developing a system level safety concepts and requirements for ADAS and IVI use cases with customer implementations in mind and to integrate Qualcomms hardware in leading Automotive OEM and Tier 1 safety critical systems. Work in collaboration with 3rd party, Customer, and Automotive Stack suppliers, Hardware component suppliers (PMIC, DRAM, Sensor, etc) to ensure all aligned customer system level requirements are met Work with IP and SoC teams on the implementation of Technical Safety Concepts (TSCs) on Qualcomms Snapdragon automotive hardware. Work with various technology teams on architectural features that would enable targeted safety levels (ASIL B to ASIL D, depending upon the technology team and system level requirements) to meet customer targets Conducting safety analyses, both quantitative and qualitative, fault campaigns on automotive hardware designs and identify areas of improvement. Responsibilities will include leading functional safety related activities for SoC development and ensure ISO 26262 compliance with respect to SoC architecture, development processes and work products. Work closely with SoC Design and IP teams, Software team, Quality teams, the functional safety manager(s) as well as customers to ensure the functional safety process is executed and documented. Working with vendors and partners to ensure functional safety requirements are fulfilled by the components that they provide Work with internal and external functional safety assessors to ensure compliance with ISO 26262 Create functional safety collateral for customers viz. Functional Safety Manual, Safety Analyses Reports, dedicated application notes etc. Supporting customer assessments of our safety features and recommending HW and SW based solutions that meet overall system targets. Working closely with customers and supporting them on various functional safety related aspects Minimum Qualifications Bachelors degree in engineering, Information Systems, Computer Science, or related field. 8+ years Systems Engineering, SoC Integration, Verification, or related work experience. Collaborative work experience with good communication skills involving customers, vendors, and internal development teams. Structured problem-solving capability and ability to work with teams on root cause analyses. Preferred Qualifications 5+ years Automotive experience and familiarity with Safety work products, experience with Functional Safety Hardware and/or Software development in semiconductor industry meeting IS0 26262/ IEC 61508 standards. Prior automotive experience in ADAS and self-driving systems preferred. System level Functional safety analysis experience on Hardware/Software components integration preferred SoC/IP integration or verification with good understanding of SoC Architecture and IP design experience preferred Management Tools and establishing traceability for functional safety requirements e.g. DOORS, etc. Familiarity with Failure Modes and Effect Analysis (FMEA) and Fault Tree Analysis (FTA) is required experience using tools to perform FMEA, FTA preferred Familiarity with hardware failure rate calculation (FMEDA) experience using Siemens 29500 and/or IEC 62380 preferred Relevant Safety Certification is desired e.g. CFSE, CFSP

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Overview: Person will be responsible for developing next generation SoCs for mobile products and its adjacencies. The role will require the candidate to understand and work on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. The person is also responsible for overseeing physical design and verification aspects. : - Full chip design for multi million gates SoC- Digital design and development (RTL)- Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification- Manage IP dependencies, planning and tracking of all front end design related tasks- Driving the project milestones across the design, verification and physical implementations Minimum Qualifications: - Minimum 15 years of solid experience SoC design- Developing architecture and micro-architecture from specs- Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC- Understanding of Memory controller designs and Microprocessors is an added advantage- Understanding of Chip IO design and packaging is an added advantage- Familiarity with various bus protocols like AHB, AXI is highly desired- Ability to review top level test plans- Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC- Working knowledge of timing closure is a must - Should have good post silicon bring up and debug experience - Should have good SoC integration exposure and its challenges - Should have good exposure to design verification aspects - Having SoC specification to GDS to commercialization experience is highly desired - Needs to makes effective and timely decisions, even with incomplete information.- Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas.- Provides direction, mentoring, and leadership to a small to medium sized groups.- Should possess strong communication and leadership skills to ensure effective communication with Program

Monitor,analyze security events,alerts across various platforms. Investigate potential security incidents,escalate as appropriate,following defined incident response processes. Correlate events from multiple sources to identify patterns or anomalies Required Candidate profile Lead,participate in threat hunting activities to proactively identify potential threats vulnerabilities Serve as the administrator for SOC tools including SIEM, EDR, SOAR,threat intelligence platforms Perks and benefits To be disclosed post interview

5-6 years of hands-on experience with IBM QRadar admin Fine tuning Strong understanding of SIEM, network security, and log management. troubleshooting QRadar issues, DSM management, and offense tuning Basic scripting knowledge (e.g., Python, Shell)

Pre-Silicon Validation Engineer Experience4 to 10 Years QualificationB.E / B. Tech / M.E / M. Tech Essential Duties & Responsibilities: Creating test environments, checker strategies, and test generators for validating embedded power management firmware in the SOC Communicating effectively, coordinating and working with firmware developers and SOC integration teams Potentially participating in the debug of failures in silicon and developing new testing strategies to detect these failures on pre-silicon models Mentoring junior members of the team in their development You should have 3-5 years of experience in the following areas: SoC development, verification, or integration using Verilog/SystemVerilog/OVM/UVM Reading and interpreting technical specs and Register Transfer Level (RTL) code SW development skills (Unit Testing, Test Driven Development) Hands-on Debug Preferred Skills and Experience: Expertise in any of one domain like Audio, Performance, power management will be a huge plus 4+ years’ experience with writing validation plans and implement those validation plans Job Category VLSI (Silicon engineering) Job Location FinlandOulu IndiaBangalore IndiaChennai IndiaHyderabad IndiaNoida Malaysia S. KoreaSeoul USATexas Location - Bengaluru,Chennai,Hyderabad,Noida

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Bachelor or Master degree from a top-tier institute. 6-11 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job Requirements Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA.

Drive and lead execution with SOC teams for Design. Drive efficiency on execution of SOC for integration as well as various quality checks like lint, CDC, RDC, Synthesis, CLP, LEC, constraints quality checks. Drive quality and timely delivery to various teams like DV, DFT, Emulation & PD. Work with architecture team on high level arch and uArch definition. Work with IP team for IP requirement, deliverables and negotiations. Drive SOC from concept to productization. Work with customer requirements on product definition, feature, bounding box analysis and drive optimal solution. Work with business and design team on optimal development cost solution considering in die size, power, performance optimization. Work with program management team for SOC planning, schedule, resource demand/supply, critical path analysis, dev cost and execution. Work with SOC (Design, DFT, DV, PD), System and SW team to deliver next generation high performance SOC designs. Work with post-Si team to drive Si bring up and ramp to productization. Drive improvisation on methodologies in SOC design. Get technical alignment with experts across geographies. Develop plans and track progress to maintain aggressive development timelines. Has understanding on SOC and IP development milestones and drive execution to meet them. THE PERSON: Strong understanding of SOC design methodology & related flows. (Design integration including UPF, Lint, CDC, RDC, CLP, LEC). Also on various handoffs (DV, PD, DFT & Emulation) Leader with strong self-driving ability and winning attitude. Be able to drive technical alignment with experts across geographies to improve design methodologies. Strong interpersonal and stakeholders management skills. Strong problem-solving skills. Strong commitment to own/drive SOC development using well-defined metrics. Work with PM team on execution planning, to track quality metrics, milestone convergence, to assess risk, and ensure plan is on track. Detail-oriented candidate who can work seamlessly with larger SOC design team across geographies on driving the solutions. Technical Leader with strong self-driving ability and winning attitude. Should have excellent communication written, oral and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. KEY RESPONSIBILITIES: Driving SOC design execution across from concept to tape-out and productization. Contribute to Bounding box analysis, Design, DFT, Verification, Test-plan, Power Reduction, Timing Convergence & Floorplan, Tape-outs, System engineering and SW deliverables. Running regular execution meetings, scrums, standing meetings and resolving bottlenecks. Project planning, schedule, deliverables, risk/ mitigations. Presenting status update to senior executives. Good understanding of sign-off flows like Lint, CDC, RDC, Formal Equivalence, Low Power Checks, timing convergence (both tile-level and FCT), and full chip integration flows. Drive and improvise various design hand-offs to DV, DFT, PD and Emulation teams. Understanding design requirements, timelines and various milestones of a project and tracking project convergence status accordingly covering all aspects of the design cycle. Drive methodology development ideas/forums. Collaborate with CAD and EDA vendors to further strengthen AMD and S3 design methodology. Strong interpersonal skills to work across teams in different geographies. Provide technical direction, guidance, and Support to the engineering team. PREFERRED EXPERIENCE: Experience of successfully leading multiple SOC execution from spec to tape-out and productization. Expertise in SOC integration and implementation - IP Integration, SOC fabrics, Voltage / Clock domain crossings, DFT, Power intent design, RTL Quality checks, Clock, Reset, Fuses, Synthesis, Timing Analysis, Design Partitioning, PPA optimization, PnR, Timing analysis, Floorplan convergence, Physical design implementation and signoff. Experience in ASIC execution, customer engagement, deliverables and execution flow. Work with a team of Architects, Hardware and Software engineers to define the High-Level Architecture. Strong hands-on experience in different SOC design activities, Verification aspects, Test plan review, Debug/triage, bottleneck resolution etc. Strong Problem Solving and Debugging Skills Comfortable with design/implementation tools and flows like VCS, SOC Connectivity, Spyglass Lint/CDC/RDC, VCLP, Synthesis DC/FC, ICC, and Physical design implementation/signoff tools, STA and constraints analysis tools. Expertise in SOC architecture, System bus and IO protocol understanding (e.g. AXI, PCIe, Memory, uProcessor, etc.) Good understanding of System integration, multi-die methodology, packaging, yield, and system solution. Experience in working with SW team for BIOS, FW, Driver, SW stack, QA and SW release is a plus. Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks, and mitigation plan. Good understanding of Power, Performance and Area (PPA) optimization techniques. Good experience with Perl/TCL/Shell/Python scripting, and Verilog/VHDL RTL design. Excellent presentation and inter-communication skills. ACADEMIC CREDENTIALS: ~5+ years of strong experience in leading end to end SOC design and ASIC execution. BE/B.Tech/ME/MTECH/MS or equivalent ECE/EEE with 12+ yrs. of experience