AMS Verification Engineer - System Verilog

We are looking for 2 AMS (Analog Mixed Signal) verification engineers who possess more than 5 years of experience, have hands-on RNM modeling exposure, and are well-versed with Cadence AMS/DMS Flow. As an AMS Verification Engineer, you should have the following skills: - Strong RNM modeling skills. - Proficiency with Cadence AMS/DMS flow. - Experience with SystemVerilog and Verilog-AMS. - Knowledge of analog and mixed-signal design principles. - Experience with UVM (Universal Verification Methodology). - Ability to debug AMS modeling issues. - Experience with basic scripting/automation. - Good communication and documentation skills. Your responsibilities will include: - Developing and executing verification plans for AMS designs. - Creating and automating testbenches for AMS verification. - Building and maintaining SystemVerilog real number models. - Working with analog and digital design teams to ensure designs meet specifications. - Verifying AMS/DMS IP/chip functionality. If you meet the above requirements and are eager to contribute to a dynamic team, we would like to hear from you.,