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6+yrs -Senior Design Verification Engineer - Virtual drive - 7th June

6 - 10 years

11 - 21 Lacs

Posted:3 weeks ago| Platform: Naukri logo

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Full Time

Job Description

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

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HCLTech
HCLTech

Information Technology Services

New Delhi

210,000+ Employees

1020 Jobs

    Key People

  • C Vijayakumar

    CEO
  • Kalyan Kumar

    Corporate Vice President & Chief Technology Officer

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