0.0 - 1.0 years

0 - 3 Lacs

Bengaluru

Hybrid

Job Description: Very important: Vehicle knowledge (the more the better) Knowledge of Driver assistant functions (ADAS, Powertrain, ) themselves as well as how they are supposed to work/what they should do Proper, fluent English in written and spoken form Interest in the Technology, Motivation, Discipline and Honesty Important: Knowledge in EXAM Testbench (HIL) knowledge Vehicle bus-protocol knowledge (not the details, just the broad idea what a bus is and how it is used for communication) Knowledge on ECU flashing guidelines and therefore knowledge of ODIS ControlDesk Knowledge Useful: German A2+ Python Willingness to travel for onsite training if necessary

Posted 1 week ago

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QA Engr - Engine COP Testing, leading German OEM at Oragadam, Chennai Bhava Business Consultants

3.0 - 7.0 years

5 - 8 Lacs

Chennai

Work from Office

1) Plan and execute Engine CoP testing 2) Co-ordinate internal & external stakeholders for CoP selection 3) Responsible for clearance of tested parts & engines 4) Plan and monitor assets of engine CoP test equipments/instruments 5) Support to team in risk assessment and in critical topics 6) Report test result to management 7) Responsible for conversion and scrap reduction Quality assurance process in Engine CoP: 1) Execute Quality process in Engine CoP: 2) Execute activities control plan acc.to standards/ procedures/ authority specific requirements 3) Ensure adherence of processes(retro fitment, engine clearance) and control plan. 4) Arrange meeting with homologation team and update necessary documents/ plan activities accordingly. 5) Responsible for Managing of CoP folders and data 6) Responsible for payment clearance of test agency 7) Responsible for E sticker verification activities 8) Support to team in Issue resolution and work on action item 9) Support to team in failures investigation and work on action item.

Posted 2 weeks ago

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6+yrs -Senior Design Verification Engineer - Virtual drive - 7th June HCLTech

6.0 - 10.0 years

11 - 21 Lacs

Hyderabad, Chennai, Bengaluru

Work from Office

Role & responsibilities Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies 5-7 years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment

Posted 3 weeks ago

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