ASIC/RTL Design Engineer

As a DV Engineer at our company, you will be responsible for a range of tasks related to logic design, RTL coding, SoC design, and integration for complex SoCs. Your main responsibilities will include: - Understanding the standards and specifications to ensure compliance with the latest methodologies. - Developing verification IPs and defining Functional Coverage matrix and Comprehensive Test plan. - Managing regression and functional coverage closure. - Integrating and verifying DUT for IP delivery sign-off. - Leading a small team of engineers. To excel in this role, you must possess the following qualifications: - Strong experience in Logic design and RTL coding, SoC design, and integration. - Proficiency in Verilog/System-Verilog and UVM. - Knowledge of AMBA protocols such as AXI, AHB, APB, and SoC clocking/reset architecture. - Hands-on experience with tools in ASIC development like Lint and CDC. - Experience in Multi Clock designs, Asynchronous interface, ECO fixes, and formal verification. - Familiarity with System Verilog Assertions and scripting for automation. Your person skills should include excellent oral and written communication, proactive attitude, creativity, curiosity, motivation to learn, and good collaboration skills. Desired skills and experience for this role include prior experience as a Design Verification Engineer and a background in developing Verification IPs. Please note: The company's additional details were not provided in the job description. As a DV Engineer at our company, you will be responsible for a range of tasks related to logic design, RTL coding, SoC design, and integration for complex SoCs. Your main responsibilities will include: - Understanding the standards and specifications to ensure compliance with the latest methodologies. - Developing verification IPs and defining Functional Coverage matrix and Comprehensive Test plan. - Managing regression and functional coverage closure. - Integrating and verifying DUT for IP delivery sign-off. - Leading a small team of engineers. To excel in this role, you must possess the following qualifications: - Strong experience in Logic design and RTL coding, SoC design, and integration. - Proficiency in Verilog/System-Verilog and UVM. - Knowledge of AMBA protocols such as AXI, AHB, APB, and SoC clocking/reset architecture. - Hands-on experience with tools in ASIC development like Lint and CDC. - Experience in Multi Clock designs, Asynchronous interface, ECO fixes, and formal verification. - Familiarity with System Verilog Assertions and scripting for automation. Your person skills should include excellent oral and written communication, proactive attitude, creativity, curiosity, motivation to learn, and good collaboration skills. Desired skills and experience for this role include prior experience as a Design Verification Engineer and a background in developing Verification IPs. Please note: The company's additional details were not provided in the job description.