Functional Verification Engineer

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Role Summary

Functional Verification Engineer

Key Responsibilities

• Develop and maintain

  block-level testbenches

  using SystemVerilog/UVM.
• Create and execute

  verification plans (V-Plans)

  , run regressions, and drive

  coverage closure

  .
• Work on testbenches with

  Real Number Modelling (RNM)

  .
• Perform

  netlist and gate-level simulations (GLS)

  .

Qualifications & Experience

• Education:

  Bachelor’s degree or higher in Electronics or related field.

• Experience:

  5–10 years in Functional Verification.

Technical Skills

• Strong hands-on coding experience in

  SystemVerilog/UVM

  .
• Proven experience in

  block/IP-level verification

  ; subsystem/SoC-level experience is an added advantage.

Soft Skills

• Strong communication skills.
• Ability to work independently and meet delivery schedules.

Strict Checklist (Must-Have Requirements)

✔ Pure DV role with expertise in developing TB environments and components

0-delay and timing simulations

Real Number Models

IP verification coverage closure

6+ years