1277 System Verilog Jobs - Page 5

As a Senior Verification Engineer at NVIDIA's CPU verification team, you will have the exciting opportunity to work on cutting-edge CPUs that power the next generation of self-driving cars, including high-end SoCs like Xavier. Xavier features a custom "Denver" class CPU designed to deliver exceptional performance while meeting automotive standards such as ISO26262. In this role, you will collaborate with a team of talented engineers to verify micro-architecture and architecture features at various levels, ranging from unit to subsystem and full chip testbenches, including FPGA and Silicon. You will also have the chance to work closely with CPU architects to develop verifiable designs and contribute to full-stack development, ensuring that sequences are verified at the software simulator level and successfully implemented on silicon with a complete software stack. The ideal candidate for this position should have strong verification fundamentals and the ability to seamlessly transition between working on software simulators and silicon. Proficiency in CPU architecture, particularly ARM knowledge, as well as experience with Verilog, System Verilog, and excellent debugging skills are essential. Additionally, candidates should possess a minimum of 3 years of experience in Computer Science, Electronics Engineering, or related fields at the Bachelor's or Master's level. To truly stand out in this role, you should have experience working on diverse CPU unit/microarchitecture verification projects, demonstrate expertise in coverage-driven verification, and showcase a track record of successful collaboration with geographically diverse multi-functional teams. At NVIDIA, we offer competitive salaries, a comprehensive benefits package, and an inspiring work environment that attracts some of the most talented individuals in the industry. If you are a creative and autonomous engineer with a genuine passion for technology, we invite you to join our rapidly growing, best-in-class engineering teams and make a meaningful impact in the world of CPU verification.,

As a Principal Engineer - ASIC Verification at Micron Technology, you will be an integral part of a highly skilled ASIC Team working on cutting-edge technology nodes. Your primary responsibility will be to lead the IP verification process, from creating test plans to achieving signoff. You will play a crucial role in ensuring the first-pass product through comprehensive verification coverage, including mixed-mode verification. Additionally, you will be involved in mentoring and coaching junior team members and collaborating with domain specialists globally on core technical initiatives. To excel in this role, you should possess a good understanding of DDR-PHY, LPDDR5/DDR4/5/HBM protocols and have experience in verifying complex high-speed PHY and/or AMS IPs. Your track record should demonstrate the ability to build test plans and UVM environments from scratch, as well as expertise in RTL debugging, scoreboarding, and code coverage analysis. Proficiency in System Verilog and UVM Methodology is essential, along with excellent written and verbal communication skills. This position requires a strong commitment to working in cross-functional and globally dispersed teams. Ideal candidates for this position will hold an M.S./M.Tech or BS/BE degree in Electronics and have at least 10 years of relevant experience. If you are passionate about pushing the boundaries of memory and storage solutions and thrive in a dynamic and innovative environment, Micron Technology offers a unique opportunity to be part of a global leader in the industry. Micron Technology, Inc. is dedicated to transforming the way information is used to enhance life for individuals worldwide. With a focus on customer satisfaction, technological leadership, and operational excellence, Micron delivers a diverse range of high-performance DRAM, NAND, and NOR memory and storage products under the Micron and Crucial brands. Our innovations power the data economy, driving advancements in artificial intelligence, 5G applications, and more from the data center to the intelligent edge. To explore career opportunities at Micron Technology, please visit micron.com/careers. For any assistance with the application process or to request reasonable accommodations, please contact hrsupport_in@micron.com. Micron Technology upholds a commitment to prohibiting the use of child labor and adheres to all relevant laws, regulations, and international labor standards within the industry.,

You will be joining as a Senior FPGA Engineer professional at our Bangalore location with a minimum of 5 years of experience. In this role, your primary responsibilities will include collaborating with a team of product managers, developers, and testers to define feature requirements, developing feature specifications, and implementing detailed designs using Verilog and FPGA design tools. You will also be involved in problem isolation, fault finding in embedded systems, customer issue replication, and creating/updating release notes. Additionally, you will work closely with onsite and offsite development teams to deliver market-leading products globally and mentor junior engineers in development, code, and debugging. To excel in this role, you must be an expert Verilog/System Verilog developer with strong embedded debugging skills. Proficiency in AMD/Xilinx FPGA with Vivado/Vitis tool-chains for implementations and validation, as well as experience with Xilinx/AMD simulator/ModelSim for unit and system-level simulations, is essential. You should possess excellent analytical skills, adaptability to ambiguity and change, and a thorough understanding of the FPGA development cycle within project-based environments. Experience with modern 32-bit processors/microcontrollers like ARM, debuggers, protocol analyzers, and logic analyzers is required. Desirable skills include expertise in Embedded Linux Kernel and Device Drivers development, familiarity with video and audio codecs such as MPEG4 and JPEG, knowledge of USB protocols, and understanding of network protocol stack concepts like ethernet, IP, and TCP. Strong communication and documentation skills are necessary for this role. If you are interested in this opportunity, please share the following details along with your profile to vijitha.k@blackbox.com: - Total experience: - Relevant experience in FPGA: - Experience in Embedded: - Experience in Linux: - Current CTC: - Expected CTC: - Notice period: - Current Location: - Preferred Location: - Current Company: - Any pending offers: - Educational Qualifications,

You will be responsible for joining OnSemi's growing team in Bengaluru, India as a Sr. Principal Digital Design Engineer focused on New Product Development in Power Management. Your primary responsibilities will include working on the development of various Power Management products for consumer, industrial, and automotive applications such as DC-DC PMIC/POL, multiphase controllers, drivers, converters, LED drivers, SiC drivers, switches, and efuses. Your key responsibilities will involve collaborating with different product lines for RTL implementation of power convertor controller designs, working on digital design architecture, RTL, low power design, synthesis, and timing analysis. You will also interface with the Physical Design team for the power management chips using state-of-the-art RTL2GDS flows. As part of a large engineering team, you will collaborate effectively with design architects, digital verification, project management, and digital and analog design teams across various global locations. You will be involved in micro-architecture to RTL implementation, supporting system-level bring-up on pre-silicon platforms, and owning the technical outcome of Power Management ICs. Furthermore, you will be responsible for understanding project goals, executing with realistic schedules, reporting progress status, and supporting post-silicon validation activities. You will also lead and support customer issues, production issues, FW and system development, and failure analysis. Onsemi is a company driving disruptive innovations to create a better future, focusing on automotive and industrial end-markets. With a highly differentiated product portfolio, Onsemi aims to solve complex challenges and lead the way in creating a safer, cleaner, and smarter world. To qualify for this role, you should have a BS in Electrical Engineering or related field with 12 years of experience, or an MS with 10 years of experience in Digital Design, Architecture, and ASIC/Mixed signal chip developments. The ideal candidate will possess a thorough understanding of the end-to-end digital design flow, RTL design, CDC, ASIC synthesis, timing analysis, P&R, UPF, system Verilog, Verilog, TCL, and Perl/Python/XML programming languages.,

You should have a minimum of 5 years of experience in developing FPGA-based prototype platforms. Your expertise should include proficiency with Xilinx (AMD) Vivado toolchain and implementation flow, as well as Synopsys/Mentor FPGA synthesis flow. It is essential to have a good understanding of Virtex-7, Virtex Ultrascale, and Virtex Ultrascale+ Architectures. In addition, you must be proficient in Verilog/System Verilog/VHDL and have a working knowledge of C/C++. Experience in using validation environment test equipment such as Logic Analyzers, Oscilloscope, Protocol Analyzers, etc. is required for this role. Having prior experience in working on ARM core architectures would be considered an advantage for this position.,

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, you enable customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, there is quite a lot to offer. Join a team that blurs the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow's idea - it is what we make real for our customers today. Siemens EDA, a global technology leader in Electronic Design Automation software, empowers companies worldwide to develop highly innovative electronic products faster and more efficiently. Siemens EDA's Questa Simulation Product is a core R&D team working on multiple verticals of Simulation. The team is characterized by its energy and enthusiasm, comprising motivated individuals based in Noida, with opportunities for travel to other locations in India and globally. As part of this team, you will contribute to impacting entire cities, countries, and the shape of things to come. Responsibilities: - Collaborate with a senior group of software engineers on core algorithmic advances and software design/architecture within the QuestaSim R&D team of Siemens EDA. - Contribute to final production level quality of new components and algorithms, as well as create new engines and support existent code. - Demonstrate self-motivation, self-discipline, and the ability to set personal goals, working consistently towards them in a dynamic environment to enhance your success. Required Experience: - A graduate with at least 2 years of relevant working experience and a degree in B.Tech or M.Tech in CSE/EE/ECE from a reputed engineering college. - Proficiency in C/C++, algorithm and data structures, Compiler Concepts and Optimizations. - Experience with UNIX and / or LINUX platforms is essential. - Basic Digital Electronics Concepts are a plus. - Knowledge of Verilog, System Verilog, VHDL, parallel algorithms, job distribution, ML/AI algorithms, and their implementation in data-driven tasks. - Exposure to Simulation or Formal based verification methodologies is beneficial. - Self-motivated, ability to work independently, guide others towards project completion, strong problem-solving, and analytical skills. Siemens is a collection of over 377,000 minds building the future, one day at a time in over 200 countries. The company is dedicated to equality, encouraging applications that reflect the diversity of the communities it works in. Employment decisions at Siemens are based on qualifications, merit, and business needs. Bring your curiosity and creativity to help shape tomorrow.,

The role of (VLSI) Design Verification (DV) involves working on functional specifications of IPs, subsystems, and SOC. You will be responsible for reviewing and revising designs, utilizing System Verilog and UVM for verification. Your tasks will include performing RTL simulations using Synopsys and Cadence simulators, as well as working with UPF. We are looking for candidates who can join immediately and hold a degree in BE, B.Tech, ME, or M.Tech. This position is based in Bangalore, Hyderabad, Kochin, and Pune. If you are interested in this opportunity, please reach out to us at career@krazymantra.com.,

You will be part of the Intel Core Design Team driving Intel's latest CPUs in the world's leading process technologies. As a Pre-Silicon Verification Engineer, you will develop pre-Silicon functional verification tests to ensure that the system meets design requirements. Your responsibilities will include creating test plans for RTL validation, defining and running system simulation models, and implementing corrective measures for failing RTL tests. You will also analyze results to modify test benches and tests to improve validation plans. As a Pre-Silicon Verification Lead/Architect, you will lead and guide a team to develop complex pre-Silicon verification environments, verification components, and coverage plans. You will drive strategic initiatives related to tools, methodologies, and quality to reduce the overall cycle time of validation projects. Working closely with hardware architects and logic designers, you will influence SoC and system design to ensure product success. Additionally, you will provide technical leadership, manage resources, and drive engineering activities to meet schedules, standards, and cost. To qualify for this role, you must possess a master's degree in Electronics or Computer Engineering with at least 4 years of experience or a Bachelor's Degree with at least 10 years of experience in Pre-Silicon Verification Environment. Preferred qualifications include experience with RTL design, Verilog, System Verilog based verification techniques, CPU architecture/Processor Verification, Perl/Python, Linux OS, SVTB UVM, or Specman (e). You should be a team player with excellent self-motivation, communication, problem-solving, and teamwork skills. The Client Computing Group (CCG) at Intel is responsible for driving business strategy and product development for PC products and platforms. As part of this group, you will contribute to delivering purposeful computing experiences that unlock people's potential. This role is an Experienced Hire position based in India, Bangalore, and eligible for a hybrid work model that allows splitting time between on-site and off-site work.,

XIMAX SOLUTIONS in Bengaluru is passionate about talent acquisition, HR consultancy, and career development. We specialize in connecting the right talent with the right opportunities, fostering meaningful relationships, and guiding professionals towards fulfilling careers to drive success and unlock potential. We have the following job opportunities available: **Job 1: Verification Engineer (ARM CPU Based Sub-System, C Programming)** - **Location:** Bangalore - **Experience Required:** 7+ years - **Employment Type:** Full-time **Key Skills & Requirements:** - Expertise in verifying ARM CPU-based sub-systems - Proficiency in C programming - Strong knowledge of verification methodologies - Experience with System Verilog and UVM - Ability to create and execute test plans - Excellent debugging and analytical skills **Job 2: Verification Engineer (SV & UVM)** - **Location:** Bangalore - **Experience Required:** 5+ years - **Employment Type:** Full-time **Key Skills & Requirements:** - Proficient in System Verilog and UVM. - Strong knowledge of verification methodologies. - Experience with simulation and debugging tools. - Ability to create and execute test plans. - Excellent problem-solving and analytical skills. - Strong communication and teamwork skills. If you meet the requirements for either of these positions and are interested in joining our team, please send your resume to ramya@ximaxsolutions.com by 7th October 2024. Join us at XIMAX SOLUTIONS and be a part of the future of semiconductor innovation! Apply here: [Job Application Form](https://forms.gle/b15i5gFeFb9jnN7D9),

Position : ASIC Design Verification Engineer Requirements : 2Years to 15Years experience in SystemVerilog/UVM-based verification for IP/SoC Skills in assertions, formal verification and emulation Experience with high-speed interfaces (PCIe, DDR, Ethernet), scripting (Python, TCL, Perl) and working across cross-functional teams Responsibilities : Full verification closurefrom test planning and testbench development to formal, emulation-based verification and ensuring first-pass silicon success Role & responsibilities Preferred candidate profile

Core Technical Skills : SystemVerilog / UVM testbench and coverage methodologies Constraint-random verification, simulation and debug flow Formal verification techniques (e.g. Jasper, VC Formal) Scripting languages: Python, TCL, Perl, Shell Experience with high-speed protocols (PCIe, DDR, Ethernet) and emulation tools Resume & Interview Prep Advice : Highlight projects involving ASIC/SoC verification, testbench implementation, coverage closure using UVM/SystemVerilog Reddit+15Reddit+15Meta Careers+15Indeed+8Atos Jobs+8Indeed+8Reddit+1Indeed+1Reddit+2Meta Careers+2Reddit+2Reddit+2Reddit+2Reddit+2 Showcase contributions in debugging RTL, developing functional coverage models, and scripting automation for regressions Next Steps Role & responsibilities Preferred candidate profile

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, 10 years of experience with Camera ISP image processing or other multimedia IPs such as Display or Video Codec, 10 years of experience with System Verilog Assertions (SVA), assertion-based verification, and formal verification, 4 years of experience in people management, developing employees, Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, Experience in low-power design verification, Experience working with RTL design and integration teams on methodologies that improve team productivity and velocity, Experience working with software teams to define hardware/software interfacing including control/status registers, security, and error handling, About The Job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration, Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology, Responsibilities Lead a team of individuals; set and communicate individual and team priorities that support organizational goals Meet regularly with individuals to discuss performance and development, and provide feedback and coaching, Work cross-functionally to debug failures and verify the functional correctness of the design, Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use, Plan the verification of complex Camera ISP hardware IPs at subsystem and full chip level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios, Create and enhance constrained-random verification environments using System Verilog and UVM, Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form , Show

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers.

Challenging and Interesting work on building and enhancing Indias only completely open-source RISC-V based SHAKTI processors. Learn everything about the entire flow from spec to silicon. Work on state-of-the-art research topics and engineering efforts. Exposure to engage with foreign universities and support in preparation to pursue higher studies in India/Abroad. Exposure to engage with leading industry partners thereby improving your career trajectory and exposure. International Publications can also be achieved as part of tenure, boosting your research potential for higher studies. Required Skill Set Must have basic expertise in at least one of: verilog, vhdl, bluespec system verilog and/or chisel. Must have knowledge: digital design, pipelining Basic computer architecture knowledge, include one or more of : in-order cores, out-of-order cores, processors, caches, SoC development, memory architecture, etc. Good to have experience with FPGAs , performance modelling, workload analysis/benchmarking, python scripting, knowledge of peripheral and communication IPs

•BE/B.Tech in ECE /M.Tech in VLSI with 6 to 9 years experience in Analog Mixed Signal Verification •Very Good experience in Verilog AMS, Verilog-A, WREAL, modeling of Analog blocks •Very Good experience in Analog Mixed Signal verification simulation tools •Good experience in System Verilog, UVM methodologies •Able to train the team members and guide them to the solutions for problems •Good experience in creating the AMS Verification environment and able to create AMS Verification environment from scratch. •Good experience in Gate level netlist simulation •Experience in Python, Perl, Shell scripting is added advantage. •Good communication and documentation skills

Job Titles: Senior Staff ASIC RTL Design Engineer Bangalore location We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a passionate and highly skilled digital design engineer with a strong background in ASIC RTL design You thrive on technical challenges, enjoy collaborating with global teams, and are motivated by seeing your designs come to life in real-world products With over8 years of hands-on experience in architecting, implementing, and verifying complex digital systems, you are adept at translating functional specifications into efficient, robust RTL Your experience spans data path and control path designs, and you are comfortable working with industry-standard protocols such as Ethernet, DDR, PCIe, USB, and AMBA You possess deep expertise in synthesizable Verilog/SystemVerilog, design flows, and EDA tools You are equally at home mentoring junior engineers as you are diving deep into code or debugging complex issues Your ability to balance area, latency, and throughput trade-offs sets you apart, and your attention to detail ensures high-quality, reliable IP cores You communicate effectively with both technical and non-technical stakeholders and are comfortable engaging with customers to clarify requirements and ensure successful delivery You value diversity, inclusion, and continuous learning, and you bring a collaborative spirit to every project If youre ready to lead, innovate, and make a tangible impact in the world of high-performance silicon design, Synopsys is the place for you, What Youll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for high-performance synthesizable IP cores within the DesignWare family, Translating complex functional and standard specifications into detailed architecture and micro-architecture documents for medium to high complexity blocks, Owning the entire digital design lifecycle, including RTL coding, synthesis, CDC analysis, debugging, and test development, Collaborating with global, multi-site teams of expert engineers to drive technical excellence and innovation, Interacting with customers to understand and refine specification requirements and providing technical guidance as needed, Mentoring and technically leading junior designers, fostering growth and sharing best practices within the team, Participating in design reviews, quality process improvements, and ensuring adherence to industry-leading verification and design methodologies, The Impact You Will Have: Delivering robust, high-quality IP cores that power next-generation commercial, enterprise, and automotive applications worldwide, Driving innovation in digital ASIC design, enabling faster, more efficient, and reliable silicon solutions for Synopsys customers, Contributing to the advancement of industry standards and protocols through technical leadership and deep domain expertise, Enhancing team performance through mentorship, knowledge sharing, and technical guidance, Strengthening Synopsysreputation as a leader in chip design by consistently delivering on complex customer requirements, Accelerating product development cycles by streamlining design processes and championing best-in-class methodologies, What Youll Need: Bachelors or Masters degree in EE, EC, or VLSI with8+ years of relevant industry experience in digital ASIC RTL design, Expertise in data path and algorithmic block design ( e-g , Reed Solomon FEC, BCH codes, MAC SEC engines) and architecture trade-offs, Proficiency in synthesizable Verilog/SystemVerilog RTL coding, simulation, and EDA tools, Hands-on experience with design flows including Lint, CDC, synthesis, static timing analysis, and formal checking, Strong knowledge of industry-standard protocols (Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA AXI/AMBA2), Experience with high-speed design (>600MHz), P&R aware synthesis, and tools like Fusion Compiler is a significant plus, Familiarity with revision control systems ( e-g , Perforce) and scripting languages (Perl/Shell), Prior experience as a technical lead or mentor within a design team is highly desirable, Who You Are: A collaborative team player who thrives in a global, distributed environment, An effective communicator, adept at conveying complex technical ideas to diverse stakeholders, A proactive problem-solver with strong analytical skills and high initiative, Detail-oriented, quality-focused, and committed to delivering excellence, Passionate about mentoring and enabling the growth of others, Dedicated to diversity, inclusion, and fostering an open, respectful workplace, The Team Youll Be A Part Of: Youll be an integral member of the DesignWare IP Design R&D team at Synopsys Bangalore, collaborating with some of the brightest minds in the industry The team is focused on developing cutting-edge synthesizable IP cores that are deployed in a wide range of commercial, enterprise, and automotive applications Working in a multi-site, global environment, youll have opportunities to engage with cross-functional teams, contribute to technical excellence, and drive innovation in digital design, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process, Show

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. Your role will involve RTL Design and implementation of interface logic between PCIe controller and DMA engines for high-performance networking applications. You will be creating block-level micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance throughout the design flow. In addition to your technical responsibilities, you will also need to work and communicate effectively with multi-site teams. Your experience in ASIC product life cycle, including requirements, design, implementation, test, and post-silicon validation, will be essential in this role. If you are passionate about technology solutions and enjoy working in a collaborative environment, we encourage you to apply for this position. Join us at MarvyLogic and be a part of building futuristic and impactful solutions that make a difference in various industries. Your experience with emerging technologies and your contributions to our team may help you evolve both professionally and personally, leading to a more fulfilling life.,

As part of a diverse team at Google, you will be working on developing custom silicon solutions for direct-to-consumer products. Your role will involve contributing to the innovation that drives products loved by millions globally, shaping the future of hardware experiences with a focus on performance, efficiency, and integration. You will specifically be involved in the development of a cutting-edge Application-specific integrated circuit (ASIC) aimed at accelerating machine learning computation in data centers. Working collaboratively with various teams such as architecture, verification, power and performance, and physical design, you will be responsible for specifying and delivering high-quality designs for next-generation data center accelerators. Your problem-solving skills will be put to the test as you tackle technical challenges using innovative micro-architecture and practical logic solutions, while evaluating design options with considerations for complexity, performance, power, and area. The Technical Infrastructure team at Google is responsible for the architecture that supports everything users see online. From maintaining data centers to building future Google platforms, this team plays a crucial role in enabling Google's product portfolio. As part of this team, you will be involved in defining and driving the implementation of physical design methodologies, taking ownership of design partitions or top-level, ensuring the closure of timing and power consumption aspects of the design, contributing to design methodology, libraries, and code reviews, as well as defining physical design-related rule sets for functional design engineers.,

At Cadence, we are dedicated to hiring and nurturing leaders and innovators who are eager to leave a mark on the technology industry. With over 30 years of expertise in computational software, Cadence stands as a pivotal figure in electronic design. Our Intelligent System Design approach helps us provide software, hardware, and IP solutions that bring design ideas to life. Our clientele comprises the most groundbreaking companies globally, creating exceptional electronic products across various sectors such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and healthcare. The Cadence work environment offers a multitude of benefits: - A chance to engage with cutting-edge technology and a culture that fosters creativity, innovation, and impact-making. - Employee-centric policies that prioritize physical and mental well-being, career growth, learning opportunities, and acknowledging achievements based on individual needs. - The "One Cadence One Team" ethos that encourages collaboration within and among teams to ensure customer satisfaction. - A range of learning and development avenues tailored to cater to employees" specific interests and requirements. - Collaborating with a diverse team of enthusiastic, committed, and skilled individuals who consistently go the extra mile for customers, communities, and each other. Job Summary: We seek a professional with over 14 years of experience possessing the following skill set: - Proficiency in RTL design basics utilizing HDLs like VHDL/Verilog/System Verilog. - Comprehensive understanding of AMD (Xilinx) Ultrascale, Versal FPGAs architecture, and experience with Vivado for FPGA place and route. - Competence in defining constraints for FPGAs and conducting Static Timing Analysis. - Familiarity with FPGA prototyping or emulation is advantageous. - Eagerness to learn and explore new technologies, showcasing strong analytical and problem-solving abilities. - Effective written and verbal communication skills, a quick learner, and a team-oriented individual. At Cadence, we are committed to impactful work. Join us in unraveling challenges that others find insurmountable.,

Qualcomm India Private Limited is seeking a Hardware Engineer with expertise in complex high-performance RTL design, particularly on DSP or processor based sub-systems. You should be proficient in hardware design using Verilog, System Verilog, or VHDL and have knowledge of on-chip bus interface protocols like AXI, APB, and AHB. Experience in model development (SystemC, or C++), RTL to gates synthesis (Synopsys DCG or Cadence Genus), design rule and CDC checking (SVA assertions, Spyglass, 0-in), and working on high-performance low power RTL design is essential. Familiarity with scripting languages such as PERL, Python, TCL, C, etc., is also required. As a Hardware Engineer at Qualcomm, your responsibilities will include developing micro-architecture, designing and documenting specific ASIC modules, and sub-systems. You will own the RTL, ensuring its development, assessment, and refinement to meet power, performance, area, and timing goals. Troubleshooting architecture, design, or verification issues using sound ASIC engineering practices, and leveraging various design tools to enhance design quality will be part of your role. Additionally, you will collaborate with the design verification team to execute the functional verification strategy and contribute innovative ideas for IP core and process flow enhancements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 2 years of Hardware Engineering experience. Alternatively, a Master's degree with 1+ years of relevant experience or a PhD in a related field will also be considered. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by emailing disability-accommodations@qualcomm.com or calling Qualcomm's toll-free number. The company expects all employees to adhere to applicable policies and procedures, including those related to security and protection of confidential information. Please note that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities at Qualcomm. Staffing and recruiting agencies are not authorized to use the site for submissions. Unsolicited resumes or applications from agencies will not be accepted. For further information about this role, reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is looking for a Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge, world-class products. Collaboration with cross-functional teams will be essential to meet performance requirements and develop innovative solutions. To be considered for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 3 years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience will also be considered. You should have 2-6 years of experience in Synthesis, Constraints, and interface timing Challenges, along with a strong domain knowledge in RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System Verilog, micro-architecture & designing cores and ASICs, and familiarity with Synthesis, Formal Verification, Linting, CDC, Low Power, UPFs, etc., will be highly beneficial. Exposure in scripting languages such as Pearl/Python/TCL and strong debugging capabilities are also required for this role. As a Qualcomm Hardware Engineer, you will collaborate closely with cross-functional teams to research, design, and implement performance, constraints, and power management strategies for the product roadmap. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require an accommodation during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. If you are a proactive team player with the ability to independently debug and solve issues, and meet the qualifications mentioned above, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

You are a highly experienced RTL Design Engineer with 12-20 years of experience, specializing in PCIe IP development. Based in Noida/Bangalore, you will be responsible for designing and supporting the RTL of Cadence's PCIe IP solution. Your role will involve working with existing RTL, adding new features, ensuring customer configurations are clean, supporting customers, and ensuring design compliance with LINT and CDC guidelines. To qualify for this position, you must hold a BE/BTech/ME/MTech degree in Electrical/Electronics/VLSI and have extensive experience as a design and verification engineer, with a focus on RTL design using Verilog. Additionally, you should have experience with System Verilog, UVM-based environments, AXI3/4/5, and preferably PCIe. Previous experience in RTL design of complex protocols and IP development teams is highly advantageous. As a member of the Cadence High-Speed SerDes PHY IP Front end Design team, you will be responsible for defining microarchitecture, leading ASIC design, collaborating with cross-functional teams, mentoring junior members, and fostering a high-performance team culture. Requirements for this role include a Bachelor's degree in Electronics Engineering with at least 7 years of experience, a Master's degree with 5 years, or a Ph.D. with 2 years in Digital Design. You should have hands-on experience in micro-architecting digital blocks, RTL implementation in Verilog/SV, SDC definition, STA, Lint Checks, CDC, and Synthesis. Knowledge of protocols such as Ethernet, USB, PCIe, MIPI(DPHY), and HDMI/Display is desired, along with the ability to work closely with Analog design teams and develop high-speed critical digital circuits and signal processing blocks.,

Exp 5-10 yrs NP: Immediate to 45 days Location : Pune/Bangalore Contract role Skills : system Verilog, PCIe, Ethernet, verification JD: You will implement simulation testbenches, low power simulation setup, assembly/C language diagnostics, assertion checkers or coverage monitors to meet target verification goals. You will also assist with developing test-plans, debugging failures and analyzing coverage information. Must have excellent knowledge of computer architecture and design verification fundamentals Must have experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies Must have experience in developing complex test bench in System Verilog using OVM/UVM methodology Hands-on experience in AMBA protocol, PCIe MAC, USB MAC, Bluetooth MAC, Wifi 802.11 MAC layer protocol Experience in Low Power Simulation/UPF setup, debug low power simulation failures. Exposure to scripting languages like Perl, Unix shell or similar languages Good to have some experience with assembly language programming required Excellent written and oral communication skills necessary. Interested candidates can send me your resume to Renuka@Sincera.in

You should have a minimum of 6-8 years of total work experience with specific expertise in the following areas: - Experience working with USRP N310/X310 (N3xx/X3x0) - In-depth knowledge of FPGA Architecture - Proficiency in writing custom RTL HDL or integrating IP, including VHDL, Verilog, SystemVerilog, Vivado HLS, Xilinx IP, and Vivado Block Diagram - Development experience with RFNoC Blocks - Familiarity with USRP Hardware Driver (UHD) - Ability to write custom FPGA logic in RFNoC Blocks and utilize existing RFNoC Blocks library (e.g., FFT, FIR, Signal Generator, Fosphor) - Understanding of the GNU Radio interface to RFNoC Block - Skills in FPGA debugging and hardware/software integration - Knowledge of appropriate coding styles for FPGAs and trade-offs for density and speed - Thorough understanding of Xilinx ZYNQ 71xx/PL-KINTEX-7-based RFNoC architecture - Capability to comprehend customer requirements, define architecture, and create detailed designs - Strong communication skills to interact effectively with customers - Familiarity with Agile methodology - Bachelor of Engineering or Bachelor of Technology degree (B.E./B.Tech.) This is a full-time, permanent position with a day shift schedule. The role requires individuals with a notice period of up to 30 days. The work location is in person. If you meet the specified qualifications and experience requirements, please apply for this role.,

As a software engineer in the QuestaSim R&D team at Siemens EDA, you will have the opportunity to work on core algorithmic advancements and software design/architecture. Collaborating with a senior group of software engineers, you will play a key role in ensuring the final production level quality of new components and algorithms, as well as in creating new engines and supporting existing code. Your self-motivation, self-discipline, and ability to set personal goals will be essential in contributing to your success in a dynamic environment. Siemens EDA is a global technology leader in Electronic Design Automation software, enabling companies worldwide to develop innovative electronic products efficiently. With a focus on pushing the boundaries of technology in chip, board, and system design, our tools play a crucial role in delivering high-quality products in a complex technological landscape. We are looking for a graduate with a minimum of 2 years of relevant working experience and a degree in CSE/EE/ECE from a reputable engineering college. Proficiency in C/C++, algorithms, data structures, and Compiler Concepts and Optimizations is required. Experience with UNIX and/or LINUX platforms is crucial, along with a solid understanding of Basic Digital Electronics Concepts. Knowledge of Verilog, System Verilog, VHDL, parallel algorithms, job distribution, ML/AI algorithms, and their implementation in data-driven tasks is highly valued. Exposure to Simulation or Formal based verification methodologies would be a plus. The ideal candidate should be self-motivated, capable of working independently, guiding others towards project completion, and possessing strong problem-solving and analytical skills. Join our team at Siemens, where over 377,000 minds collaborate globally to shape the future, one day at a time. We are committed to diversity and equality in our workplace, and we welcome applications from individuals who reflect the communities we serve. If you are curious, creative, and ready to contribute to building tomorrow's innovations, we invite you to join us.,