1272 System Verilog Jobs

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus.

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Board Design. Experience: 3-5 Years.

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: Mechanical Part design. Experience: 3-5 Years.

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. • Expertise emulation / prototyping using Cadence / Synopsys tool flows • Expertise in Palladium / Protium / HAPS / Zebu tools • Expertise in System Verilog & Verilog language semantics and compilation flows • Expertise on AXI protocol • Good Knowledge on SOC architecture

Job Description: SOC Verification engineers with 3+ years of experience Knowledge of ARM architecture, CPU fundamentals & Cache coherency Experience with C/C++, assembly, and scripting languages. Familiarity with low-power design and verification Develop CDV UVM verification environments at system level Verify CPU connectivity to IP blocks Develop SoC test plans and test cases and track metrics including code and functional covera Job Requirement: Bachelors or Masters in EE/CS or related field 3+ years of SoC in ASIC/FPGA verification experience Proficiency in SV and UVM Experience with simulation, emulation, and formal verification Strong debugging and problem-solving skills Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Looking for Siemens EDA ambassadors We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and better? Join us whichever path you take, were looking forward to seeing your point of view! This is your Role! We are looking for a highly motivated Senior and Lead Member Technical Staff engineers to work in the Calypto Design Systems Division. You will be part of a high-performing PowerPro R&D software team responsible for designing, developing, and debugging software programs for the industry standard Power Optimization and Formal Verification tool development team at Siemens EDA. Team up with a senior group of software engineers and give to final production level quality of new software features, components, and algorithms and to support existing software components. We are not looking for superheroes, just super minds We seek a Graduate / Post Graduate (Bachelors/Masters) in EEE) / ECE/Computer Science (CS) from top reputed Engineering colleges with 5-8 years of significant experience in software development. Experience in EDA will be a plus! We value a sound understanding of C/C++ languages, design patterns along with data structure and algorithms will be key to development of software. We appreciate an understanding of HDL languages Verilog/VHDL/System Verilog s needed. Knowledge of scripting languages, hands-on knowledge of Revision control systems like Perforce will only improve the development time. Good analytical, abstraction and communication skills helps in creating bigger and balanced solutions for complex systems. Ability to work with multi-functional teams as a teammate will help in creating good solutions that resolve actual customer issues.

Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills. Who You'll Work With Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

Looking for Siemens EDA Ambassadors- QuestaSim (Simulation) R&D team (strong AI/ML background) This is your role In this role, you will, craft and develop AI/ML-driven algorithms and solutions to improve simulation tools' performance and capabilities. Contribute to building state-of-the-art engines and components, integrating machine learning techniques into simulation and verification workflows. Contribute to the development and improvement of production-quality components, algorithms, and engines while supporting and improving existing codebases. Solve complex, open-ended problems in collaboration with a senior group of engineers in a fast-paced and multifaceted environment. Apply technical expertise in AI/ML frameworks, data-driven problem solving, and traditional simulation technologies to achieve project milestones. Stay self-motivated, disciplined, and focused while driving innovation within the team. Required Qualifications We are seeking a graduate with Bachelors or Masters degree in Computer Science, Artificial Intelligence, Electrical Engineering, or a related technical field from an accredited institution. We value your experience with conceptualizing, defining, architecting, and implementation of an open-ended problem scope or new insights. Hands-on experience with AI/ML techniques, including supervised and unsupervised learning, neural networks, and reinforcement learning. Strong proficiency in programming languages like C/C++ and Python, along with strong foundations in algorithms and data structures. Knowledge of machine learning and deep learning frameworks. Strong understanding of Compiler Concepts, Optimizations, and parallel computing. Experience working on UNIX and/or LINUX platforms. Excellent problem-solving and analytical skills. Proven track record to work independently, take ownership of tasks, and deliver results A plus! Basic knowledge of Digital Electronics and concepts related to SystemVerilog, Verilog, and VHDL. Exposure to Simulation technologies or Formal-based Verification methodologies is a plus!

Software Engineer- C Programming,Networking platform development, PHY drivers, SERDES, SFP Meet the Team The Enterprise Switching organization delivers top-tier products, with the Catalyst Cat9000 series leading in core, aggregation, and access switching for security, IoT, and Cloud. These switches are critical for SD-Access, Cisco's intent-based networking architecture, offering the bandwidth, speed, and scale needed for hybrid work environments. They improve security with PoE power and AI/ML for zero-trust security and provide outstanding network experiences both on-premises and in the cloud through Cisco DNA Center or the Meraki Dashboard. The new Catalyst 9000X models offer flexible operations and secure, high-speed performance. Our team is world-class for crafting industry-leading products that have dominated the enterprise market for decades through innovation. Your Impact Looking forward to getting an exciting start to your career? You will bring your outstanding talents to the group that works on Cisco's Switching technology, which large enterprises now consider to be the Networking Equipment of choice for critically important networks. In your role as a Software Engineer, you will develop and integrate products that are deployed by some of the leading Enterprises in the world. You will work with a BU-wide vibrant technical community, learning from experts and translating this learning into exciting opportunities for personal growth. You will work on networking equipment that forms a crucial backbone of many offices, hospitals, educational and financial institutions. You will learn about pioneering technologies and platforms while developing software for these equipments. Experience the exhilaration of taking a product through development and integration. Minimum Qualifications Good understanding of distributed/centralized hardware architectures of routers/switches. Experience in working with embedded platforms, various operating systems viz Linux, VxWorks , RTOS internals. Have worked on various Device drivers viz PCIE/I2C/eMMC/SDHC/MDIO/USBs and have worked on Storage devices NAND/NOR with exposure to file system internals. Exposure to system infrastructure - Building and bringing up next generation sophisticated Switches. Experience - 4 to 8 years Bachelors degree or equivalent experience in CS/EE/EC or technical equivalent. Preferred Qualifications: Bachelors degree in computer science or related field (MS or equivalent preferred).

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As a DFT Engineer, you will be responsible for developing and implementing Design for Test methodologies for complex VLSI designs. You will ensure the testability and manufacturability of our products by working closely with design, verification, and physical design teams, while employing state-of-the-art techniques to optimize coverage, cost, and performance. Responsibilities: 1. Develop and implement DFT architectures and strategies for complex SoC designs. 2. Insert and verify DFT features such as scan chains, Built-In Self-Test (BIST) for memory and logic, and boundary scan (IEEE 1149.1/1149.6). 3. Perform ATPG (Automatic Test Pattern Generation) and analyze coverage metrics to ensure high fault coverage. 4. Collaborate with RTL designers to ensure seamless integration of DFT features into the design. 5. Debug and resolve test-related issues in simulation, silicon validation, and production. 6. Work closely with the physical design team to implement scan and clock constraints for timing closure. 7. Optimize test time, power, and cost without compromising coverage and quality. Participate in silicon bring-up and post-silicon validation activities. 8. Generate and maintain DFT documentation, including test plans, methodologies, and results. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 2-10 years of experience in DFT for VLSI designs. Strong knowledge of DFT methodologies, including scan insertion, BIST, and ATPG. 3. Experience with EDA tools such as Synopsys Tetramax/DFTMax, Cadence Modus, or Mentor Tessent. Proficiency in 4. Verilog/SystemVerilog and scripting languages (Python, TCL, Perl). 5. Solid understanding of STA concepts and constraints related to DFT. 6. Experience in debugging silicon and ATE test patterns. Knowledge of test standards like IEEE 1149.x (JTAG) and 1500. 7. Excellent problem-solving skills and ability to work in a collaborative environment. Preferred Qualifications: 1. Experience with low-power DFT techniques. 2. Familiarity with fault diagnosis and yield improvement methodologies. 3. Exposure to advanced nodes (7nm, 5nm, or below) and FinFET technologies. 4. Knowledge of machine learning or AI techniques for test optimization. 5. Hands-on experience with multi-core and hierarchical DFT architectures. Why Join Us? 1. Be part of a team driving innovation in the semiconductor industry. 2. Work on challenging and impactful projects in a supportive environment. 3. Opportunities for career advancement and skill development. 4. Competitive salary and comprehensive benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 8+/6+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills.

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

We are looking for a skilled RTL Design Engineer with 3 to 7 years of experience to join our team at Capgemini Technology Services India Limited. The ideal candidate will have a strong background in IT Services & Consulting and be proficient in RTL design. Roles and Responsibility Design and develop high-quality RTL code for various projects. Collaborate with cross-functional teams to identify and prioritize project requirements. Develop and maintain technical documentation for RTL designs. Troubleshoot and debug issues related to RTL code. Participate in code reviews and ensure adherence to coding standards. Stay updated with industry trends and emerging technologies in RTL design. Job Requirements Strong understanding of digital logic design principles and methodologies. Proficiency in programming languages such as Verilog or VHDL. Experience with RTL design tools and software. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment. Strong communication and interpersonal skills.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

We are looking for a skilled DFT Engineer with 3 to 7 years of experience to join our team in the IT Services & Consulting industry. The ideal candidate will have a strong background in designing and implementing fault detection and testing strategies. Roles and Responsibility Design and develop test plans, test cases, and test scripts for complex systems. Collaborate with cross-functional teams to identify and prioritize testing requirements. Develop and maintain automated testing frameworks and tools. Analyze test results, identify defects, and work with development teams to resolve issues. Participate in agile development methodologies and contribute to process improvements. Stay up-to-date with industry trends and emerging technologies in DFT engineering. Job Requirements Strong understanding of digital logic design principles and microelectronic circuits. Experience with programming languages such as C++, Python, or Java. Familiarity with testing frameworks like JUnit, PyUnit, or Selenium. Knowledge of version control systems like Git. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment and communicate technical ideas clearly.

As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: 1. Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. 2. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. 3. Perform design optimizations for area, power, and performance. 4. Conduct design reviews and ensure compliance with coding standards and best practices. 5. Work closely with verification teams to develop test plans and ensure 100% functional coverage. 6. Debug and resolve design and integration issues during simulation and post-silicon validation. 7. Participate in timing analysis and closure in collaboration with the physical design team. 8. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 210 years of experience in RTL design and implementation for VLSI systems. 3. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. 4. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. 5. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. 6. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. 7. Experience in static timing analysis (STA) and timing closure workflows. 8. Strong problem-solving skills and the ability to debug complex design issues. 9. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: 1. Experience with low-power design and multi-clock domain systems. 2. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 3. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. 4. Familiarity with machine learning or AI-based RTL optimizations. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future.

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As a Design Verification Engineer, you will be responsible for verifying complex SoC designs, working closely with design teams to ensure robust and high-quality products. You will employ advanced verification methodologies and tools to identify and resolve issues, ensuring that our SoC designs meet industry standards and customer requirements. Responsibilities: 1. Develop and execute comprehensive test plans to verify the functionality of SoC designs. 2. Create and maintain verification environments using advanced verification techniques, such as UVM, SystemVerilog, and assertion-based methodologies. 3. Collaborate with design teams to debug and resolve functional issues in RTL and gate-level simulations. 4. Ensure thorough verification coverage by analyzing and improving functional coverage metrics. 5. Perform regression testing to ensure consistent performance and reliability across design iterations. 6. Work closely with architects and designers to understand design specifications and refine verification strategies. 7. Develop reusable verification components and ensure alignment with project timelines and quality standards. 8. Document verification results, generate detailed reports, and present findings to stakeholders. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2. 3+ years of experience in SoC design verification within the VLSI domain. 3. Expertise in advanced verification methodologies, including UVM and SystemVerilog. 4. Strong understanding of SoC architectures, protocols, and interfaces (e.g., AXI, PCIe, USB, DDR). 5. Proficiency with simulation tools such as VCS, ModelSim, or Questa. 6. Experience with scripting languages (Python, Perl, TCL) for automation. 7. Familiarity with version control systems like Git. Excellent debugging and problem-solving skills, with a focus on delivering high-quality results. 8. Strong communication and collaboration skills to work effectively with cross-functional teams. Preferred Qualifications: 1. Experience with formal verification tools and techniques. 2. Familiarity with low-power verification strategies. Knowledge of hardware-software co-verification. 3. Exposure to machine learning or AI-based approaches in verification. Why Join Us? 1. Work on state-of-the-art SoC designs in a collaborative and innovative environment. 2. Opportunity to be part of a fast-growing company shaping the future of VLSI solutions. 3. Competitive compensation, professional growth opportunities, and a supportive work culture. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future !

Starting business in a new village a. Village identification within the radiusb. Feasibility study of the village based on demographics, activities and financial needs ofthe customersc. Assist the MC-IC in making the village approval Sourcing of business a. Identification of customers and forming of Joint Liability Groupsb. Filling up of the application formc. Verification of the residence and business of the customerd. KYC verificatione. Pre-disbursement trainingf. Visiting potential customers in order to develop business Disbursements a. Collection of KYC documentsb. Assisting the MC-IC for disbursement activity completionc. Loan documentation Collection of current dues a. Collect the collection sheets and stickers from MC-ICb. Group-wise collection as per scheduled time by following the processc. Deposit of collection moneyd. MERC entry Collection of over dues a. Follow up with the customers with updated data report of assigned portfoliob. Collection of money as per processc. Depositing the money in bankd. MERC entrye. Assist the MC-IC in initiating action against the defaulters Eligibility: Interested in Sales and Collections Graduate / Post Graduate / 12 th / DiplomaTwo-Wheeler (Driving License / LLR Mandatory) Pan Card Age 21 Years to 32 Years Other Benefits Group Life Insurance + Group Personal Accident Cover

Starting business in a new village a. Village identification within the radiusb. Feasibility study of the village based on demographics, activities and financial needs ofthe customersc. Assist the MC-IC in making the village approval Sourcing of businessa. Identification of customers and forming of Joint Liability Groupsb. Filling up of the application formc. Verification of the residence and business of the customerd. KYC verificatione. Pre-disbursement trainingf. Visiting potential customers in order to develop business Disbursements a. Collection of KYC documentsb. Assisting the MC-IC for disbursement activity completionc. Loan documentation Collection of current duesa. Collect the collection sheets and stickers from MC-ICb. Group-wise collection as per scheduled time by following the processc. Deposit of collection moneyd. MERC entry Collection of over dues a. Follow up with the customers with updated data report of assigned portfoliob. Collection of money as per processc. Depositing the money in bankd. MERC entrye. Assist the MC-IC in initiating action against the defaulters Eligibility: Interested in Sales and Collections Graduate / Post Graduate / 12 th / Diploma Two-Wheeler (Driving License / LLR Mandatory) Pan Card Age 21 Years to 32 Years Other Benefits Group Life Insurance + Group Personal Accident Cover

This Position reports to: Senior Designer Your role and responsibilities In this role, you will have the opportunity to create and modify the standard designs of equipment, systems, or installations, including standard specifications for manufacturing, fabrication, or construction, using standard design concepts. Each day, you will design engineering solutions, including drawings and calculations according to contract specifications. You will also showcase your expertise by contributing to design reviews and design verification and modifying the design, as necessary. The work model for the role is: #LI-Onsite This role is contributing to the Electrification business in Distribution Solutions division at Nashik, India . You will be mainly accountable for: Contributing to the preparation of specific aspects of design assignments to meet the contractual obligations, adhering to relevant standards, safety, cybersecurity, and quality requirements. Ensuring that Bill of Materials for the project meets contractual obligations and project gross margin requirements by not generating Project Left-Over Material. Coordinating with manufacturing and testing functions to ensure the designs are appropriately manufactured / staged and tested, updating the engineering deliverables as built. Using standard processes and tools and assisting in developing new processes and tools for the reuse of technical solutions. Our team dynamics You will join a high performing team, where you will be able to thrive. Qualifications for the role You are engaged with Design Function in Switchgear Industry You have 3 to 6 years of experience in Designing of Medium Voltage Switchgear (AIS) You have hands on experience in preparing Bills of Material, Schematics, Single line diagram (SLD) and Manufacturing releases Possess an enhanced knowledge of Eplan Degree in Electrical Engineering (should be full-time) You are at ease communicating in English.

Performs functional logic verification of an FPGA to ensure design will meet specification requirements Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs Replicates, root causes, and debugs issues in the pre-silicon environment Finds and implements corrective measures to resolve failing tests Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features May also collaborate with systems and software engineers to support integration testing of the FPGA Documents test plans and drives technical reviews of plans and proofs with design and architecture teams Maintains and improves existing functional verification infrastructure and methodology Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e g , gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Run IO PHY tests with AMS (Digital/Analog Mixed Signal Simulation). Collaborates and communicates with Architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Qualifications Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/with: Pre Silicon Validation/Verification. JESD 79-5 DDR5, JESD209-5 LPDDR5, JESD 209-4 LPDDR4, DDR PHY Interface (DFI 5.1) Tessent SSN scan OVM/UVM, System Verilog, constrained random verification methodologies

Skills/Experience: Extensive experience in IP/SOC Verification. Must be proficient in System Verilog and UVM. Must have hands-on experience in the verification of the IP protocols such as PCIe/DDR/USB/Ethernet/CXL/HDMI/MIPI/DSI/CS/GLS/CPU Verification or any other high-speed protocols. Experience with scripting language (Python, Perl, TCL etc.) Experience in assembly language or C is a plus. Ability to create testbenches from scratch and own the complete verification including coverage of the subsystem/chip level. Strong debugging capabilities. Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Skills/Experience: Proficient in Scan, specializing in ATPG and Pattern verification at Block and Full chip level. Skilled in Scan insertion, ATPG, DRC analysis, Low Coverage Analysis, JTAG and IJTAG. Experienced in scripting for flow automation, using Siemens tools (Tessent), Synopsys tools (DFTMAX, Tetra MAX, VCS, DFT Compiler), Verdi. Familiar with tools: NC-SIM/Irun, Sim-Vision, XCELIUM. Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent