1277 System Verilog Jobs - Page 2

Starting business in a new village a. Village identification within the radiusb. Feasibility study of the village based on demographics, activities and financial needs ofthe customersc. Assist the MC-IC in making the village approval Sourcing of businessa. Identification of customers and forming of Joint Liability Groupsb. Filling up of the application formc. Verification of the residence and business of the customerd. KYC verificatione. Pre-disbursement trainingf. Visiting potential customers in order to develop business Disbursements a. Collection of KYC documentsb. Assisting the MC-IC for disbursement activity completionc. Loan documentation Collection of current duesa. Collect the collection sheets and stickers from MC-ICb. Group-wise collection as per scheduled time by following the processc. Deposit of collection moneyd. MERC entry Collection of over dues a. Follow up with the customers with updated data report of assigned portfoliob. Collection of money as per processc. Depositing the money in bankd. MERC entrye. Assist the MC-IC in initiating action against the defaulters Eligibility: Interested in Sales and Collections Graduate / Post Graduate / 12 th / Diploma Two-Wheeler (Driving License / LLR Mandatory) Pan Card Age 21 Years to 32 Years Other Benefits Group Life Insurance + Group Personal Accident Cover

This Position reports to: Senior Designer Your role and responsibilities In this role, you will have the opportunity to create and modify the standard designs of equipment, systems, or installations, including standard specifications for manufacturing, fabrication, or construction, using standard design concepts. Each day, you will design engineering solutions, including drawings and calculations according to contract specifications. You will also showcase your expertise by contributing to design reviews and design verification and modifying the design, as necessary. The work model for the role is: #LI-Onsite This role is contributing to the Electrification business in Distribution Solutions division at Nashik, India . You will be mainly accountable for: Contributing to the preparation of specific aspects of design assignments to meet the contractual obligations, adhering to relevant standards, safety, cybersecurity, and quality requirements. Ensuring that Bill of Materials for the project meets contractual obligations and project gross margin requirements by not generating Project Left-Over Material. Coordinating with manufacturing and testing functions to ensure the designs are appropriately manufactured / staged and tested, updating the engineering deliverables as built. Using standard processes and tools and assisting in developing new processes and tools for the reuse of technical solutions. Our team dynamics You will join a high performing team, where you will be able to thrive. Qualifications for the role You are engaged with Design Function in Switchgear Industry You have 3 to 6 years of experience in Designing of Medium Voltage Switchgear (AIS) You have hands on experience in preparing Bills of Material, Schematics, Single line diagram (SLD) and Manufacturing releases Possess an enhanced knowledge of Eplan Degree in Electrical Engineering (should be full-time) You are at ease communicating in English.

Performs functional logic verification of an FPGA to ensure design will meet specification requirements Develops FPGA verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications Executes verification plans and defines and runs system simulation models to verify the FPGA design, analyze power and timing, and uncover bugs Replicates, root causes, and debugs issues in the pre-silicon environment Finds and implements corrective measures to resolve failing tests Collaborates with FPGA architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features May also collaborate with systems and software engineers to support integration testing of the FPGA Documents test plans and drives technical reviews of plans and proofs with design and architecture teams Maintains and improves existing functional verification infrastructure and methodology Documents, reviews, and executes the verification strategy plan on different methodologies/techniques (e g , gate-level-simulation strategy, power patterns/aware simulations) used to enable feature coverage as per the microarchitecture specifications Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Run IO PHY tests with AMS (Digital/Analog Mixed Signal Simulation). Collaborates and communicates with Architects, micro architects, full chip architects, RTL developers, post-silicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Qualifications Candidate should have a BS, MS or PhD in Electrical or Computer Science Engineering or related field with 8+ years of technical experience. Related technical experience should be in/with: Pre Silicon Validation/Verification. JESD 79-5 DDR5, JESD209-5 LPDDR5, JESD 209-4 LPDDR4, DDR PHY Interface (DFI 5.1) Tessent SSN scan OVM/UVM, System Verilog, constrained random verification methodologies

Skills/Experience: Extensive experience in IP/SOC Verification. Must be proficient in System Verilog and UVM. Must have hands-on experience in the verification of the IP protocols such as PCIe/DDR/USB/Ethernet/CXL/HDMI/MIPI/DSI/CS/GLS/CPU Verification or any other high-speed protocols. Experience with scripting language (Python, Perl, TCL etc.) Experience in assembly language or C is a plus. Ability to create testbenches from scratch and own the complete verification including coverage of the subsystem/chip level. Strong debugging capabilities. Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Skills/Experience: Proficient in Scan, specializing in ATPG and Pattern verification at Block and Full chip level. Skilled in Scan insertion, ATPG, DRC analysis, Low Coverage Analysis, JTAG and IJTAG. Experienced in scripting for flow automation, using Siemens tools (Tessent), Synopsys tools (DFTMAX, Tetra MAX, VCS, DFT Compiler), Verdi. Familiar with tools: NC-SIM/Irun, Sim-Vision, XCELIUM. Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Experience with STA using Primetime and PTPX required Proficient in constraint generation. Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl scripting is required Strong problem solving and ASIC development/debugging skills. Experience with CPU micro-architecture and their critical path. Low power implementation techniques experience. High speed CPU implementation. Place and route tool experience. Constraint management tool and Verilog coding experience Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. You've sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a great teammate, resilient and sincere, Enjoy learning new things and build knowledge base in new area.

This is your role Siemens EDA SLS Bangalore group, a part of HAV Division of Siemens EDA, is looking for an engineer, who is primarily required to understand, design and implement solutions to improve the Codelink product, including new Processor support. This includes design and implementation of the functionality for the requirements in the domain, participation in design reviews and continuous improvement of product line that Siemens EDA has in this domain, interaction with co-workers and collaborators to improve the quality of the products, work with teams in different geographies and cultures. This role is based in Bangalore. But youll also get to visit other locations in India and globe, so youll need to go where this job takes you. In return, youll get the chance to work with teams impacting entire cities, countries, and the shape of things to come. We are looking out for candidates with B.Tech/M.tech or equivalent experience in Computer Science or Electronics Engineering with shown experience & strong programming knowledge in C/C++ with strong object oriented design skills. We need someone who is good in algorithm and data-structure design skills with theoretical background in analysis of algorithms. Programming knowledge of Verilog/System Verilog is required. Adept at using one or more software development methodologies such as Agile. Problem Solving and Analysis Skills is required. Technical Skills required (Desirable): Experience in software development and debug is a plus! Experience in studying and understanding technical specifications. Knowledge of computer architecture concepts, especially processors. We are looking for someone with good understanding of configuration management tools such as git. Experience with defect tracking tools such as JIRA.

Skills/Experience: Create emulation models from RTL / Netlist. Expertise in mapping designs to Zebu/Palladium/Haps emulation, improving model performance. Knowledge of the Palladium flow and experience in migrating design on Palladium. Good knowledge of runtime and debug skills. Identifying signals and taking wave dumps on palladium platforms and analyse the failures. Exposure to ARM/ARC cores and its architecture Exposure to AMBA bus architectures like AXI/AHB/APB Exposure to bug tracking tools like Jira and version control tools like Github, Bitbucket, GIT Exposure to Flash(NAND) and HDD(Hard disk) like storage technologies. Experience with Palladium like emulation platforms(Veloce or Zebu or Haps) Understanding of JTAG based debuggers Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: VLSI Board Design. Experience: 3-5 Years.

Skills/Experience: Good Experience with Xilinx FPGA. Should be well aware of RTL logic. Well versed with Vivado tool and associated IP Well versed with LUT considerations in FPGA design Well versed with FPGA simulation and testing methods Well versed with FPGA debug using Xilinx JTAG debugger Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Skills/Experience: Strong design fundamentals with hands-on experience in front-end design flows Hands-on experience in design of micro-architecture blocks, RTL coding, block-level verification. Hands-on experience in Linting, CDC analysis of reports, identify ways to fix the violations Hands-on experience in SoC/IP integration Excellent understanding of SoC components like processors, memories, peripherals, IOs Good understanding of at-least one of the protocols like UFS/PCIe/SAS/SATA/USB Experience of working with ARM or ARC (Synopsys) processors/sub-systems Experience of UPF flow, updating constraints Ability to work independently, ramp-up quickly and work with verification/validation teams for front-end flows Good experience in PERL/TCL scripting Good verbal and written communication skills are required. Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field

We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects. About the Role : You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs. What You'll Do : - Design and implement advanced System Verilog/UVM verification infrastructures - Lead verification planning and execution for complex ASIC projects - Develop comprehensive test strategies ensuring thorough design validation - Drive debug resolution through collaboration with cross-functional teams - Mentor and provide technical guidance to verification team members - Enhance and optimize verification methodologies - Own end-to-end SOC verification environments Required Skills & Experience : - BS / MS in Electrical/Computer Engineering - 2+ years of hands-on ASIC verification experience - Expert-level SystemVerilog, UVM, and object-oriented programming skills - Strong proficiency with industry tools like VCS, Xcelium, QuestaSim - Advanced debugging and problem-solving capabilities - Excellent communication and collaboration abilities - CLP and GLS - Python/Perl scripting expertise Nice to Have : - Experience with PCIe, DDR, USB, C2C - Knowledge of on-chip interconnects and processor subsystems - Background in formal verification methods - Prior experience on Emulators What We Offer : - Opportunity to work on cutting-edge semiconductor projects - Collaborative and innovative work environment - Professional growth and leadership opportunities

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including failures and debugging procedures on SharePoint/ JIRA or any other platform as directed f. Test the entire IP functionality under regression testing and complete the documentation to publish to client g. Troubleshoot, debug and upgrade existing systems on time & with minimum latency and maximum efficiency h. Write scripts for the IP i. Comply with project plans and industry standards 2. Ensure reporting & documentation for the client a. Ensure weekly, monthly status reports for the clients as per requirements b. Maintain documents and create a repository of all design changes, recommendations etc c. Maintain time-sheets for the clients d. Providing written knowledge transfer/ history of the project Mandatory Skills: FPGA Design. Experience: 3-5 Years.

SMTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD SOCs THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP/Sub-System/SOC level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environments Experienced with Verilog, System Verilog, C, and C++ Processor Micro-Architecture concepts Reset/Boot-flow/Cache Coherency/Interrupt flows knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment. Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience. Scripting language experience: Perl, Ruby, Makefile, shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering / Electronics / Electrical Engineering #LI-SR5

About the Role : We are seeking a talented Implementation Engineer to join our dynamic team. The successful candidate will be responsible for leading and executing Synthesis and STA for complex AI SOC with multi-mode and multi power domain design, ensuring the quality and reliability of our products. This is what you are responsible for : - Synthesis and STA (static timing analysis). - Ability to optimize designs for best in class in low power and high performance with logically equivalent RTL. - Professional experience with ECO implementation, both functional and timing closure. - Experience with multi-clock, multi-power domain designs and multi-mode timing constraints. - Familiarity with DFT insertion. - Familiarity with simulation, debugging tools, and working closely with Design teams. - Ability to collaborate with different functional teams like RTL Design, DFT and Physical design. - Showcase your deep understanding of the following physical design concepts/constraints: floor-planning, placement, congestion, and setup/hold timing closure. Necessary Qualifications : - Bachelor's or Master's degree in Electronics, Computer Science Engineering, or a related field - Minimum of 5 to 7 years of experience in Implementation flows/ Synthesis and STA. - Experience with Cadence, Synopsys and Mentor tools - Experience with Verilog and VHDL. - Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks (UPF/CPF/CLP) - Formal verification for RTL 2 gates and gates2gates - Conformal ECO for doing complex functional ECOs. - Low power synthesis on smaller blocks and subsystems using DC/Genus - Physical Aware synthesis - Writing Timing Constraints sub-blocks and Top level. - Flow Automation and Scripting using TCL and Python or Perl.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Developing emulation solutions for PCIe, CXL, and UCIe protocols for semiconductor customers. Engaging in software development using C/C++ and synthesizable RTL development with Verilog. Verifying solutions to ensure high performance and reliability. Interacting with customers during the deployment and debug phases to ensure smooth i mplementation. Collaborating with cross-function al teams to integrate emulation solutions. Maintaining and enhancing existing emulation solutions to meet evolving industry standards. The Impact You Will Have: Driving the development of advanced emulation solutions that meet industry standards. Enhancing the performance and reliability of semiconductor products through innovative solutions. Ensuring customer satisfaction by providing robust and efficient deployment support. Contributing to the continuous improvement of Synopsys emulation technologies. Supporting the adoption of new protocols and standards in the semiconductor industry. Strengthening Synopsys position as a leader in chip design and verification solutions. What You ll Need: 5+ years of relevant experience In-depth knowledge of PCIe, CXL, and UCIe protocols. Proficiency in C/C++ programming and object-oriente d programming concepts. Strong understanding of digital design principles and HDL languages such as System Verilog and Verilog. Experience with scripting languages like Python, Perl, or TCL. Familiarity with ARM architecture and UVM/functional verification is a plus.

Design Verification Engineer | CMAA Advisors | Careers Architect, develop, and maintain System Verilog UVM-based testbenches for Bluetooth controller IP/subsystems, including PHY/MAC/LL layers. Create comprehensive verification plans covering all Bluetooth protocol layers and custom enhancements. Verify hardware blocks implementing: Bluetooth Link Layer (LL) Baseband Controller (BBC) Adaptive Frequency Hopping (AFH) LE Advertising and Scanning HCI (Host Controller Interface) AES-CCM encryption/decryption Bluetooth Low Energy PHY (1M, 2M, Coded PHY) Develop assertions, checkers, and scoreboards for protocol compliance and functional Drive debug efforts using tools like Verdi/DVE and perform root cause analysis for RTL/test bench issues. Collaborate closely with architects, RTL, firmware, and validation teams for spec alignment and issue resolution. Ensure functional and code coverage closure; track quality metrics via regression dashboards. Handle formal review and signoff of verification deliverables, test cases, and documentation.

Strong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IJTAG. and MBIST/LBIST. Experience in Tessent based ATPG flow, GLS and Post-silicon-debug. Hands-on in Perl/Tcl/Python scripting. Excellent analytical, and problem-solving skills. Perform Core and SOC level ATPG to meet Automotive grade quality. Hierarchical ATPG retargeting and Pattern release for application on ATE. Perform SOC and Core level Timing/Non-timing GLS. Silicon bring-up, diagnosis and support for physical failure analysis. Enable Emulation of Gate level SCAN patterns. Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

The Sales Specialist works with the Lead Salesperson to meet agreed sales and revenue targets. The Sales Specialist will generate detailed client / product knowledge, market knowledge and cultivate client relationships in order to generate sales opportunities. The Sales Specialist will work to develop deep understanding of the client need / product detail and Banks capabilities with the aim of meeting client satisfaction expectations. The Sales Specialist will be conversant relevant legal, regulatory and Bank policy requirements and operate accordingly. Together with the Lead Salesperson ensure liaison with existing clients. Researching and fostering new client opportunities. Building the necessary working relationships with origination, trading, research, client services, and operations staff if applicable & to the degree that is commensurate with the business area - to ensure effective end to end client / product delivery Your key responsibilities Hunt for new client deals in cash management across MNCs and LLCs across business segments like Corporates, NBFI, New Age Companies Grow wallet from existing clients and own existing CCM client relationships including coverage at CFO/CXO levels Align sales efforts to Banks growth strategy and grow underlying revenue drivers like liabilities, overdrafts, deposits and x-border flows Commercialize innovative and new products to existing and new clients Provide deep solutioning and structuring cum advisory to clients, leveraging understanding of clients business and industry and in close coordination with Banks SMEs Work on RFPs and large complex deals in partnership with stakeholders across the Corporate Bank. Your skills and experience Existing sales background with 7-12 years workex in corporate sales Experience in Cash management sales an advantage, experience in working on other products like Trade Finance & FX and/or Coverage in Commercial/Corporate Banking is an advantage MBA from top B-Schools, CA or similar post graduation qualification from top institutions preferred Self-starter, go-getter, should have high levels of initiative, energy, enthusiasm and curiosity levels.

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug. You will play a key role in silicon bring-up, workload execution and validation. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Proficiency in C and Python for validation and automation Hands on experiencec in Writing/ maintaining test programs and automation scripts using C and Python Experience in chip bring-up /debug Experience in chip-level throttling issues including power, thermal, and frequency-related behavior Knowledge on Analyzing trace data/logs and on-chip debug outputs for failure root cause Should be able to Interpret Verilog RTL to support functional and performance debug Collaborate with RTL, firmware, validation, and DFT teams for end-to-end issue resolution Strong understanding of chip boot flows and bring-up sequences Familiarity with assembly-level debugging on RISC/V, ARM, or other architectures Ability to read and debug Verilog RTL code In depth understanding of chip internals, including resets, clocking, and register programming Preferred technical and professional experience Experience in post-silicon validation, emulation or pre-silicon environments Exposure to firmware-hardware interactions Knowledge of debug infrastructure and on-chip monitoring tools Familiarity with version control tools like Git

Lead the Architecture, Design and development of processor MMU (Memory management unit) for high- performance IBM Systems. - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the MMU feature enhancements. - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in - 8 to 15 years of relevant experience - At least 1 generation of experience in the memory management/ memory controller delivery leadership. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. Good understanding of industry trends & advances in architecting high bandwidth memory solutions.

End-to-end design and development of features for IBM high performance Mainframe and POWER processors and ASICs. Develop the feature, present the proposed architecture in the High level design discussions Estimate the overall effort to develop the feature Develop micro-architecture, Design RTL, Collaborate with the Verification, Physical design, FW teams to develop the feature Pre Silicon: Signoff the Design that meets all the functional, area and timing goals Post Silicon: Bringup and Validate the hardware functionality Required education Bachelor's Degree Required technical and professional expertise 1 to 3 years of professional experience Experience with HDLs- VHDL/ Verilog Understand and Design Power efficient logic. Drive design closure including test plan reviews and verification coverage Understand of logic synthesis, Physical Design concepts, Timing, and constraints Prior experience in and knowledge in one or more areas : I2C, I3C, SPI, AXI, AHB, APB, boot, security, debug and trace, OTP ROM, clocks and resets, silicon bringup

Role Overview As a Senior/Lead Design Verification Engineer , you will own verification strategy and execution for high-complexity IP and SoC designs. You will be responsible for planning, leading teams, defining testbench architecture, and ensuring coverage-driven closure. Key Responsibilities Define and drive the verification plan based on design specifications and functional requirements. Architect and develop reusable UVM/SystemVerilog-based testbenches. Own IP/SoC-level functional verification from test planning to coverage closure. Work closely with RTL, DFT, and firmware teams for seamless integration and debug. Guide and mentor junior engineers; conduct reviews and knowledge sessions. Contribute to verification methodology improvements and best practices. Perform regression setup, coverage analysis, and issue tracking. Deliver high-quality, first-time-right silicon. Required Skills Strong experience in SoC verification using SystemVerilog/UVM . Solid understanding of verification methodologies and simulation flows. Hands-on with tools like VCS, Questa, Verdi, SimVision, etc. Experience with standard bus protocols like MAC (Preferred), AXI, AHB, PCIe, USB, etc. Good debugging skills using waveform viewers and log analysis. Experience in writing assertions and functional coverage models. Knowledge of scripting (Python, Perl, TCL) is a plus. Strong communication and leadership abilities. Preferred Qualifications Experience with formal verification, assertion-based verification (SVA). Exposure to low-power verification and UPF flows. Familiarity with safety/security standards (e.g., ISO 26262, DO-254). Experience working with emulation platforms and FPGA prototyping. Location: Bangalore / Hyderabad / Pune Experience: 6-12 Years Notice Period: Immediate to 30 Days Company: ADV Logics Empowering Next-Gen VLSI Innovation