1277 System Verilog Jobs - Page 4

As an ASIC RTL Engineer at Google, you will be part of a team that is dedicated to developing custom silicon solutions for Google's direct-to-consumer products. Your role will involve pushing boundaries and contributing to the innovation that drives products loved by millions worldwide. Your expertise will play a crucial role in shaping the next generation of hardware experiences, focusing on delivering unparalleled performance, efficiency, and integration. In this role, you will lead a team of ASIC RTL engineers, overseeing sub-system and chip-level integration activities. Your responsibilities will include planning tasks, conducting code and design reviews, and developing complex features. You will collaborate closely with the architecture team to develop implementation strategies that meet quality, schedule, performance, power, and area requirements for sub-system/chip-level integration. Additionally, you will work with a cross-functional team comprising Verification, Design for Test, Physical Design, and Software teams. Your role will involve making design decisions and representing project status throughout the development process. Your contributions will be essential in ensuring the successful execution of projects and meeting the goals set for each stage of development. If you have a Bachelor's degree in Electrical Engineering or Computer Science, along with 8 years of experience in high-performance design and multi-power domains with clocking, and have worked on multiple SoCs with silicon success, this role could be an exciting opportunity for you. Experience with Verilog or System Verilog language is essential, and familiarity with ASIC design methodologies for front quality checks and chip design flow will be advantageous. Join us at Google, where we combine the best of Google AI, Software, and Hardware to create radically helpful experiences. Our mission is to make the world's information universally accessible and useful, and your contributions as an ASIC RTL Engineer will play a significant role in achieving this goal.,

You should have a strong understanding of Design & Verification methodologies related to either Times or Untimed SW Models, RTL IP, VIPs, and UVM Env. It is essential to be familiar with verification tools such as Simulator and Synthesis. Proficiency in C/C++, System Verilog, UVM, SystemC, and RTL is required. Knowledge of standard protocol interfaces like AMBA, Automotive, PCIe, and USB would be beneficial. Strong written and verbal communication skills are necessary, along with the ability to work effectively both independently and as part of a team. A self-motivated attitude and a collaborative approach to teamwork are also important attributes for this role.,

Qualcomm India Private Limited is seeking a GPU Functional Verification Engineer to join the GPU HW team. As a GPU Functional Verification Engineer, you will be responsible for developing a deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities, and interfaces. Your duties will include strategizing and proposing a DV environment, developing a test bench, owning a test plan, debugging all RTL artifacts, and achieving all signoff matrices. You will collaborate with EDA vendors, explore innovative DV methodologies, and work with worldwide architecture, design, and systems teams to meet project goals. The ideal candidate should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. Strong knowledge of UVM based System Verilog TB, proficiency with formal tools, and excellent communication skills are desired. Additionally, the ability to learn, improve, and deliver is crucial for this role. The pre-Si verification team in Bangalore is heavily involved in UVM/SV based constrained random test bench development, subsystem level TB creation for GPU workload analysis, emulation platform utilization, formal tools application, power-aware simulations, and automation using Perl/Python scripts. Qualcomm also has an opening for a GPU Functional DV (Clock/Power) Verification Engineer to verify the Clock and power management module with design features for low power. The responsibilities include understanding GPU power and clock domains, owning end-to-end DV tasks, developing test plans, exploring innovative DV methodologies, and collaborating with design, silicon, and architecture teams. Applicants should have strong System Verilog/UVM based verification skills, experience with assertion & coverage-based verification methodology, and familiarity with low power design techniques. Knowledge of formal/static verification methodologies, Synopsys NLP tool, and scripting languages like Perl and Python is a plus. Qualcomm is an equal opportunity employer that provides accessible processes for individuals with disabilities. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes. For more information about these roles, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a skilled Hardware Engineer to join the Engineering Group, specifically the Hardware Engineering team. In this role, you will be responsible for developing micro-architecture and RTL design for security-related Cores, focusing on block level design. Your tasks will include enabling software teams to utilize hardware blocks efficiently and running ASIC development tools such as Lint and CDC. It will be crucial for you to report progress and communicate effectively against set expectations. As a qualified candidate, you should hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field, with a minimum of 5 years of Hardware Engineering experience. Additionally, having 5 to 10 years of work experience in ASIC/SoC Design is preferred. Proficiency in RTL design using Verilog/System Verilog and knowledge of cryptography concepts like public/private key, hash functions, encryption/signatures algorithms (such as AES, SHA, GMAC, etc.) will be beneficial for this role. Experience in Root of Trust, HW crypto accelerators, defining HW/FW interfaces, Linting, CDC, LEC, and database management flows with tools like Clearcase/Clearquest will be advantageous. Strong programming skills in Verilog, C/C++, Python, and Perl are essential. Excellent oral and written communication skills, proactive attitude, creativity, curiosity, motivation to learn and contribute, and good collaboration skills are also desired qualities. Qualcomm is an equal opportunity employer committed to providing accessible accommodations for individuals with disabilities throughout the application/hiring process. If you require assistance, please contact disability-accommodations@qualcomm.com. The company expects its employees to comply with all relevant policies and procedures, including those regarding the protection of confidential information. If you are a staffing or recruiting agency, please note that Qualcomm's Careers Site is exclusively for individuals seeking employment directly with Qualcomm. Unsolicited submissions from agencies will not be accepted. For more information about this Hardware Engineering position, please reach out to Qualcomm Careers directly.,

Qualcomm India Private Limited is seeking a skilled ASIC IP Cores Design Engineer to join their Hardware Engineering team. As a part of this role, you will be expected to work as a strong designer on peripheral IPs, providing design and microarchitecture solutions independently. Additionally, you will play a key role in guiding and mentoring junior team members and collaborating with external teams to address cross-team dependencies. Taking complete ownership of projects and driving them forward will be a significant part of your responsibilities. The ability to provide schedule estimates will be advantageous, along with prior experience in people management. To excel in this role, you should possess 3-6 years of work experience in ASIC IP cores design, with a Bachelor's degree in Electrical Engineering being required and a Master's degree being preferred. Knowledge of AMBA protocols such as AXI, AHB, and APB, as well as familiarity with SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and Ethernet, is highly desirable. Working closely with SoC verification and validation teams for pre and post-silicon debug will be part of your responsibilities. Proficiency in low power design, multi-clock designs, and asynchronous interfaces is a must. Experience in using ASIC development tools like Lint, CDC, Design Compiler, and Primetime is essential, along with an understanding of constraint development and timing closure. Proficiency in Synthesis and timing concepts will be an added advantage. You should have strong microarchitecting skills in RTL design from high-level design specifications. Excellent problem-solving abilities, effective communication, and teamwork skills are key requirements for this role. Being self-driven and capable of working with minimal supervision is crucial. Proficiency in System Verilog, Verilog, C/C++, Perl, and Python will be beneficial. The ability to lead a small design team will also be an advantage. A minimum qualification of a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 2+ years of Hardware Engineering experience, a Master's degree with 1+ year of relevant experience, or a PhD in a related field is required. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm for support. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to security and confidentiality. This is an exciting opportunity for a skilled engineer to join a dynamic team at Qualcomm. If you meet the qualifications and are excited about the prospect of contributing to cutting-edge projects, we encourage you to apply.,

Qualcomm India Private Limited is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. The WLAN PHY team in Bangalore specializes in taking WLAN PHY designs from concept to silicon independently. As a member of the team, you will be responsible for developing end-to-end Tx/Rx DSP chains, working on signal processing functions, and contributing to the development and enhancement of signal processing algorithms. Passion for the work and pride in your contributions are essential qualities we are looking for. The ideal candidate will have 1 to 3 years of experience in micro-architecting and developing complex IPs, expertise in digital design, and proficiency in RTL coding. Familiarity with RTL QA flows and proposing design alternatives to meet specifications are expected skills. Experience in leading, guiding, or managing junior team members, as well as success in taking IP designs from requirements to silicon, are advantageous. While not mandatory, experience with wireless technologies or HLS would be beneficial. Required skills include proficiency in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl, and experience in designing and debugging complex data-path/control-path IPs. Good communication, analytical, and leadership skills are essential. A Bachelor's, Master's, or PhD degree in Computer Science, Electrical/Electronics Engineering, or a related field is required, along with relevant work experience. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application and hiring process. If you would like more information about this role, please contact Qualcomm Careers.,

You will be responsible for demonstrating expertise in RTL Coding using Verilog, System Verilog, or VHDL. Your role will involve a strong understanding of FPGA flow, Logic design, and Digital design. It is essential to have knowledge in FPGA architecture and proficiency in Tcl and Python scripting. You will be conducting Vivado testing of synthesis tool and other stages. This position does not entail Silicon RTL development or any HW flow or testing. Your communication skills are crucial, as you will be expected to communicate technical information in an organized and understandable manner. A customer-oriented approach is necessary, along with a demonstrated concern and willingness to assist customers. Good organizational skills, multitasking abilities, prioritization, and activity tracking are essential. Exceptional oral and written communication skills are also required. TekWissen Group is committed to equal employment opportunities and supports workforce diversity.,

You should have a B.E./B.Tech/ME/M.Tech degree in Electronics and Communication with 3-8 years of experience in the verification domain. It is essential to possess deep protocol insight in NVMe, DDR4/5, DIMMs, HBM2/3 protocol along with hands-on experience in developing complex protocols verification components using System Verilog, Verilog, and OVM/UVM methodology. Knowledge of C/C++ is a plus. Additionally, a good understanding of simulation and/or emulation technologies with proven triage skills is required. Your responsibilities will include successfully deploying emerging protocol standards solutions for simulation and emulation platforms. You will be expected to publish success stories for each successful deployment, conduct periodic protocol spec upgrades, and provide training on the latest product offerings to field AEs for scalability in deployments. Furthermore, you will be responsible for tracking protocol evolution in standards organization meetings and sharing insights with marketing, engineering, and application engineering teams. You will also need to contribute technical publications in standards conferences like DVCon, DAC, and SNUG to promote Synopsys solutions visibility. Validating field of use by expert testing for leading-edge solutions prior to early adopter releases and effectively reviewing user APIs and test plans are crucial aspects of the role. Additionally, ensuring solutions collateral readiness by contributing/reviewing datasheets, feature-specific PDFs, and user guides is expected. Moreover, you will play a key role in driving product direction and product roadmap based on customer requirements and market size and adoption assessment. Setting up the right priorities based on business requirements will be part of your responsibilities. The role may require international and domestic travel.,

As an Electrical Senior Principal Engineer in our Electrical Engineering team in Bangalore, you will play a crucial role in the full hardware development lifecycle, from concept to production. Your expertise in system architecture definition, design, analysis, prototyping, sourcing, debugging, and validation of layouts will contribute to delivering state-of-the-art products that cater to the changing world's needs. Collaborating closely with designers, cross-functional teams within Dell Technologies, and suppliers, you will ensure that electronic designs meet various requirements, including schedule, feature set, functionality, quality, and industry standards. Join us in making a significant social impact and unleashing your potential to do groundbreaking work in the role of an Electrical Senior Principal Engineer. In this role, you will be part of the global Field-Programmable Gate Array (FPGA) team responsible for driving innovation in the hardware development lifecycle. Working with a team of experts, you will design, analyze, prototype, source, debug, and validate layouts to create cutting-edge products. Collaboration with designers and cross-functional teams will be key to ensuring that electronic designs meet stringent requirements and industry standards. Key Responsibilities: - Collaborate with front-end teams and industry partners to design next-generation HW features - Conduct feature and cost trade-off analysis and provide technical recommendations - Offer design guidance to support global teams effectively - Deliver system interfaces with design and process across extended teams - Prepare documentation for inspection and testing procedures To excel in this role, you should possess: Essential Requirements: - 12-18 years of experience in FPGA hardware verification using Verilog coding, System Verilog, and VHDL coding practices - Proficiency in UVM Verification framework, Assertion-based Verification, Code coverage, and Unit-level simulations - Expertise in digital design methods such as CDC, RDC, timing constraints definition, and static timing analysis - Experience in RTL Digital Design verification of x86 Core or ARM processor architecture - Knowledge of Peripheral Protocols like I2C, I3C, SMbus, IPMI, IPMB Desirable Requirements: - Familiarity with x86 (AMD & Intel) and ARM architecture - Deep understanding of hardware and software interactions to resolve issues effectively At Dell Technologies, we value the unique contributions of each team member and prioritize their growth and development. If you are seeking an opportunity to advance your career in a collaborative environment with cutting-edge technology, we invite you to be part of our team. Dell Technologies is committed to fostering an inclusive work environment that promotes equal employment opportunities and is free of discrimination and harassment. To learn more about our Equal Employment Opportunity Policy, please refer to the official policy document. Join us on our journey to build a future that benefits everyone, as progress requires the collective efforts of all individuals.,

As an RTL Engineering Lead at Google, you will play a vital role in driving innovation and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will be instrumental in shaping the future of hardware experiences that cater to millions of users worldwide. By leveraging your expertise, you will enhance performance, efficiency, and integration in the next generation of Google products. With a Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience, along with 6 years of hands-on experience in micro-architecture and coding, particularly in memory compression, interconnects, coherence, cache, Dynamic Random-Access Memory controller, and Physical Layer Device, you are well-equipped to excel in this role. Proficiency in Verilog or SystemVerilog language is a must to thrive in this dynamic environment. Ideally, you possess experience in high-performance design, multi-power domains with complex clocking, and have a proven track record of delivering successful SoCs. Your expertise in microarchitecture design and system design will be pivotal in developing highly optimized IPs with excellent Power, Performance, and Area (PPA) metrics. Familiarity with chip design flow and quality checks at the front end, including Lint, CDC/RDC, Synthesis, and Line Echo Cancellation, will further enhance your capabilities. In this role, you will lead a team of RTL engineers, overseeing IP development plan tasks, conducting code and design reviews, and driving the development of complex features within the IP. Collaboration with the architecture team is essential to strategize microarchitecture and coding implementations that align with quality, schedule, and PPA goals. Additionally, you will work closely with cross-functional teams, including Verification, Design for Test, Physical Design, and Software teams, to make informed design decisions and ensure project progress is effectively communicated throughout the development lifecycle. Join our diverse team of passionate individuals who are committed to pushing boundaries and creating innovative solutions that enhance the lives of people globally. Together, we aim to make technology faster, seamless, and more powerful, ultimately realizing Google's mission of organizing the world's information and making it universally accessible and useful.,

You should have a B.E./B.Tech/ME/M.Tech degree in Electronics and Communication with 3-8 years of experience in the verification domain. You must possess deep protocol insight in NVMe, DDR4/5, DIMMs, HBM2/3 protocol and hands-on experience in developing complex protocols verification components with System Verilog, Verilog, and OVM/UVM methodology, with knowledge of C/C++ being a plus. Additionally, you should have a good understanding of simulation and/or emulation technologies, with proven triage skills and familiarity with new product deployment challenges across different geographies. Scripting skills are also required for this role. Your responsibilities will include successfully deploying emerging protocol standards solutions for simulation and emulation platforms, along with publishing success stories for each successful deployment. You will also be responsible for periodic protocol spec upgrades and providing the latest product offering training to field AEs for scalability in deployments. Tracking protocol evolution in standards org meetings and sharing insights with marketing, engineering, and application engineering teams will be part of your role. Furthermore, you will be expected to contribute to technical publications in standards conferences like DVCon, DAC, SNUG to promote Synopsys solutions visibility. You will validate the field of use through expert testing for leading-edge solutions before early adopter releases and be an effective reviewer of user APIs and test plans. Ensuring solutions collateral readiness by contributing/reviewing datasheets, feature-specific PDFs, and user guides aligned with the latest release offerings is also a key responsibility. In addition, you will help drive product direction and product roadmap based on customer requirements, market size, and adoption assessment. You will need to set the right priorities based on business requirements. Traveling internationally and domestically may be required for this role.,

At Cadence, we are committed to hiring and developing leaders and innovators who aspire to create an impact in the technology industry. We are currently seeking a Lead Application Engineer for our GCS team based in Bangalore or Noida. As a pivotal leader in electronic design, Cadence leverages over 30 years of computational software expertise to deliver cutting-edge software, hardware, and IP solutions that bring design concepts to life. Our customers, who are among the most innovative companies worldwide, rely on us to deliver exceptional electronic products across various dynamic market applications. Joining Cadence offers you the opportunity to work with state-of-the-art technology in an environment that fosters creativity, innovation, and impact. Our employee-friendly policies prioritize the well-being and career development of our employees, providing ample opportunities for learning and growth. Our inclusive "One Cadence - One Team" culture celebrates diversity and equity, enabling us to innovate, grow, and succeed with our customers. As a Lead Application Engineer in the GCS Organization for MSA (Multiphysics System Analysis), your role involves collaborating with Cadence customers globally to offer post-sales technical consultation for IC level Power System analysis products. You will work closely with customers to resolve complex issues, help them leverage the latest tools, and guide them in implementing software within their design methodologies. This role allows you to broaden and deepen your technical knowledge, gain exposure to industry best practices, and contribute high-impact knowledge content. Additionally, you will have the opportunity to contribute to the development of key technology solutions and provide feedback to enhance product offerings. You will work in a supportive and flexible environment, where your success is a collective effort and passion for technology and innovation drives us forward. **Job Responsibilities:** - Provide technical support for Voltus product from the Multiphysics System Analysis (MSA) toolset, focusing on productivity and customer satisfaction - Support multiple tools/methods, requiring general domain knowledge and business experience - Assist in creating impactful knowledge content in the MSA domain - Work independently at Cadence or customer facilities to deliver quality results according to schedule requirements - Work on problems of moderate scope that may require analysis of situations, data, or tool problems **Qualifications:** - Bachelors Degree in Electrical/Electronics/Electronics and Communication/VLSI Engineering with 5-7 years of related experience - OR Masters with 3-4 years of related experience - OR PhD with 1 year of related experience **Experience And Technical Skills Required:** - 3-7 years of relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools, and Digital Physical implementation - Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals - Proficiency in debugging Low power and multiple power domain analysis for chip power integrity sign-off - Understanding of Digital design toolsets of Cadence (Genus/Innovus/Tempus/Conformal) and hardware description languages like VHDL, Verilog, System Verilog - Knowledge of TCL, Perl, or Python scripting **Behavioral Skills Required:** - Strong written, verbal, and presentation skills - Ability to establish a close working relationship with both customer peers and management - Creative problem-solving skills and ability to explore unconventional solutions - Effective collaboration across functions and geographies - Commitment to raising the bar while maintaining integrity Join us at Cadence, where we are dedicated to tackling meaningful challenges and pushing the boundaries of what is possible in technology. Let's solve problems that others can't.,

As a Python Expert for Electronic Design Automation (EDA) tool development in Bangalore, your primary responsibility will include developing EDA tools for SoC design, integration, and verification. You will be tasked with modeling hardware design problems in software and automating the process. Additionally, you will create UML models for design data and generate code from these models. Your role will also involve creating data structures to store design data, populating them with structured data such as XML or HDL-Models, and producing code based on this data. To qualify for this position, you must hold a Bachelor's or Master's Degree in Electronics & Communication Engineering or VLSI with 1-4 years of relevant experience. Proficiency in Python/C++, data structures, algorithms, and object-oriented programming concepts is essential. Exposure to Artificial Intelligence, Machine Learning, and Deep Learning concepts is highly desirable. Previous experience in designing and coding software/EDA tools and familiarity with Verilog, VHDL, System Verilog, and SystemC are required. Understanding of UML modeling language is preferred, and experience with test automation frameworks like pytest or Google Test is beneficial. Desirable skills include proficiency in C++, SoC Design, and FPGA. We are looking for candidates who are eager to learn new technologies quickly, possess strong analytical skills to assess complex situations, and excel in exchanging technical information effectively. The role also requires good reporting and presentation abilities, along with a solid understanding of internal interfaces.,

The DFX Verification Lead position is located in Bangalore and requires 4 to 8 years of experience. The ideal candidate should have a strong understanding of DFT requirements such as Scan, BIST, and JTAG Debuggers. In this role, you will collaborate with IP and integration teams to ensure the successful implementation and verification of design elements. Your responsibilities will include working closely with designers and verification engineers to guarantee functionality and design features for future projects. To excel in this role, you must have a deep knowledge of verification flows and be proficient in debugging at both SoC and system levels. Additionally, expertise in Verilog, System Verilog, or System C for test-bench/model development is required. If you are passionate about chip design and semiconductor projects, we invite you to apply for this exciting opportunity. To express your interest, please submit your resume to krishnaprasath.s@acldgitial.com.,

You are in search of an experienced senior verification engineer with over 10 years of expertise in ASIC/SOC/IP/block level functional verification utilizing system verilog/UVM. The perfect candidate for this role should possess a comprehensive understanding of UVM, advanced UVM, and system verilog. Your main responsibilities will include developing a detailed test plan, constructing a complete test-bench, and creating a robust verification environment that comprises interface agents and scoreboard in UVM. Additionally, you should have in-depth knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB. Strong debugging skills are essential to promptly address test-bench issues and failures. As part of this role, you will be accountable for verification closure by focusing on coverage and managing bug reports. Proficiency in utilizing industry-standard verification tools like Questa, VCS, or ModelSim is required. Experience with scripting languages like python, perl, or TCL for automation tasks is also beneficial. Furthermore, you will be responsible for managing a team of 6 to 7 Engineers and engaging with customers to provide task updates. Experience in collaborating with Japanese customers is a prerequisite for this position. Proficiency in the Japanese language is a mandatory skill. If you meet these qualifications and are enthusiastic about taking on these responsibilities, we encourage you to apply for this challenging and rewarding role.,

You will be joining Eximietas as a Senior Design Verification Engineer/Lead in Bengaluru with 5-15 years of experience. Your primary responsibility will be to lead the SoC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. This includes developing and implementing comprehensive verification strategies for high-speed and low-speed peripherals such as I2C, SPI, UART, GPIO, QSPI, as well as high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR, HBM. You will be conducting Gate-level simulations and power-aware verification using tools like Xprop and UPF. Collaboration with cross-functional teams, including architects, designers, and pre/post-silicon verification teams, will be crucial to ensure alignment and seamless integration of verification efforts. Your role will involve analyzing and implementing System Verilog assertions and functional coverage to ensure thorough verification of design functionality. Mentorship and technical guidance to junior verification engineers will be part of your responsibilities to elevate team performance. Leading and managing a dynamic team of verification engineers, fostering a collaborative and innovative work environment will be essential. You will also ensure that all verification signoff criteria are met, with clear and comprehensive documentation. Your dedication, work ethic, and commitment to meeting project goals and deadlines will be vital. Upholding quality standards and implementing best test practices to contribute to continuous improvements in verification methodologies will also be expected. You will work with verification tools from Synopsys and Cadence, including VCS and Xsim, and integrate third-party VIPs (Verification IP) to enhance verification coverage. To qualify for this role, you should have 5+ years of hands-on experience in SoC Design Verification and expertise in verification of high-speed SoCs and various protocols. Proficiency in System Verilog for verification, gate-level simulations, and power-aware verification using Xprop and UPF are necessary. Strong hands-on experience with VCS and Xsim from Synopsys and Cadence, mentorship experience, and demonstrated ability to work with cross-functional teams are also required. A strong understanding of verification methodologies and the ability to contribute to their continuous improvement are essential.,

As a Formal Verification Engineer at our Global Technology organization, you will be responsible for leading formal verification activities for single or multiple design blocks and IPs. This includes developing and executing formal verification strategies and test plans to ensure the correctness of designs. Your role will involve creating detailed formal verification plans, identifying design properties, and collaborating with design teams to enhance micro-architectures. You will play a key role in crafting innovative solutions to verify complex design architectures by developing reusable formal models and verification code bases. Additionally, you will mentor junior team members and provide technical leadership in formal verification methodologies, including training on industry-standard tools and techniques. Collaboration with cross-functional teams, such as design and verification, will be essential to ensure the seamless integration of formal verification into the overall verification flow. The ideal candidate for this position should possess expertise in formal verification techniques and methodologies, a strong command of System Verilog and Universal Verification Methodology (UVM), and hands-on experience with tools like Jasper or VC Formal (Synopsys). You should have the ability to develop reusable verification models and formal strategies, along with strong debugging, problem-solving, and team collaboration skills. Experience in mentoring engineers and driving technical leadership will be beneficial in this role. To qualify for this position, you should hold a Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. Join us in our dynamic team environment where you can contribute to cutting-edge technology developments and drive innovation in formal verification processes.,

Are you interested in a unique opportunity to be a part of something great Would you like to join a 20,000-member team that is at the forefront of technology that powers the world around us Microchip Technology, Inc. offers an environment of trust, empowerment, respect, diversity, and communication. You will have the chance to own a piece of a multi-billion dollar global organization and more. At Microchip, employees are part of a culture that supports growth and stability. They are engaged and motivated by a wide range of products and solutions with unlimited career potential. The nationally-recognized Leadership Passage Programs at Microchip facilitate career growth for over a thousand individuals annually. The company is committed to employee development, values-based decision making, and fostering a strong sense of community based on its Vision, Mission, and 11 Guiding Values. This commitment has earned Microchip numerous awards for diversity and workplace excellence. As a Verification Engineer at Microchip, your responsibilities will include playing a key role in block-level verification. You will develop verification test plans based on design specifications, create test environments using System Verilog and UVM methodologies, and integrate with RTL while conducting basic simulation bring-up for the design. You will be tasked with generating code/functional coverage, analyzing coverage results, correlating them with the test plan, creating multiple test cases, and launching regressions. Additionally, you will collaborate with the design team to quickly identify and resolve design issues. The ideal candidate for this role will have expertise in domains such as AHB, AXI, PCIe, USB, and Ethernet. Proficiency in Verilog and System Verilog is essential, as well as familiarity with at least one of the following methodologies: OVM, UVM, VMM. Experience with EDA tools like Questasim, VCS, NCSim, or NCVerilog is required. You should have experience in developing test bench components at both block and SOC levels, creating test plans, and writing test sequences. Knowledge of functional coverage, code coverage, and assertions (OVA, SVA, PSL) is desirable. Strong analytical, problem-solving skills, excellent written and verbal communication in English, and a passion for teamwork and excelling in a competitive environment are also essential. Qualifications for this role include a Bachelor's Level Degree (ECE, EE / preferred specialization) with more than 9 years of work experience. The role may involve up to 25% travel time. Please note that Microchip Technology Inc. does not accept unsolicited agency resumes. Kindly refrain from forwarding resumes to the recruiting team or other Microchip employees, as the company is not responsible for any fees related to unsolicited resumes. Visit our careers page to explore exciting opportunities and company perks.,

As a Senior Silicon Design Engineer (SMTS) at AMD, you will be an integral part of the GFX sub-system (Graphics Power Management) verification team. Your role will involve collaborating with lead architects and block design teams to understand the features to be implemented and verified. You will be responsible for developing robust test plans for both synthetic and real workload trace, debugging verification test failures, and ensuring that the design meets functional, performance, and power expectations. To excel in this role, you must have a strong background in ASIC design and be proficient in debugging Verilog RTL code using simulation/emulation tools. Your analytical thinking and problem-solving skills, attention to detail, and ability to work effectively with diverse teams will be crucial for success. Additionally, having good English communication skills, both verbal and written, is essential. Preferred qualifications for this position include a minimum of 12 years of experience in ASIC verification, proficiency in Verilog, System Verilog, UVM methodologies, and C/C++ programming. A solid academic background with a B.E/B.Tech or M.E/M.Tech degree in ECE/Electrical Engineering/Computer Engineering with Digital Systems/VLSI as a major is required. Candidates with graphics pipeline experience and deep knowledge of computer architecture will be given preference. Being a self-starter who can independently drive tasks to completion, while also possessing strong teamwork and interpersonal skills, is essential for this role. This position is based in Hyderabad, India. If you are looking to be part of a dynamic team that is dedicated to pushing the limits of innovation and solving the world's most important challenges, then AMD is the place for you. Join us in advancing technology and making a meaningful impact in the industry, communities, and the world.,

You are an experienced RTL/FPGA Design Engineer with a minimum of 3 - 7 years of experience in the VLSI domain. You hold a BE/B.Tech degree in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or a closely related field from a recognized university with a strong academic background. Your role will be based in Ahmedabad or Bangalore. In this role, you will be responsible for RTL programming using Verilog/System Verilog or VHDL, possessing knowledge of the complete FPGA Design Development flow. You should be proficient with FPGA Development Tools such as Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc. Additionally, you will engage in functional verification using Verilog/System Verilog or VHDL, optimize RTL code to meet timings and on-chip resources, and support all phases of FPGA-based product development activities. System Architecture Design, testing, and troubleshooting of hardware will also be part of your responsibilities. To excel in this position, you must have experience with Verilog/SystemVerilog or VHDL for design and verification, along with a deep understanding of FPGA design flow/methodology, IP integration, and design collateral. You should be capable of developing small IP blocks from scratch and conducting basic functional verification. Familiarity with protocols like SPI, I2C, UART, and AXI, as well as knowledge of Altera Quartus II Tool, Questasim, Modelsim, Xilinx tools like ISE and Vivado, and Microsemi tools like Libero, are essential. Understanding of USB, Ethernet, and external memories such as DDR, QDR RAM, and QSPI-NOR based Flash is also required. In terms of personal competencies, you should be self-motivated to learn and contribute, able to work effectively with global teams, and willing to collaborate in a team-oriented environment. Prioritization and execution of tasks to achieve goals in a fast-paced environment, along with strong problem-solving skills, are valuable assets. Your passion for writing clean and neat code that aligns with coding guidelines will be highly appreciated. If you meet these qualifications and are excited about the opportunity to work in the VLSI domain as an RTL/FPGA Design Engineer, we encourage you to apply now.,

Eridu AI India Private Limited, a subsidiary of Eridu Corporation, Saratoga, California, USA, invites highly motivated professionals to join its R&D center in Bengaluru. Eridu AI is a Silicon Valley hardware startup dedicated to enhancing training and inference performance for large AI models. By introducing innovative solutions in semiconductors, software, and systems, Eridu AI aims to optimize AI data center performance, increase GPU utilization, and reduce capex and power consumption. The company, backed by a team of experienced Silicon Valley executives and engineers, offers a unique opportunity to work on cutting-edge technology in the AI networking industry. As a Senior Manager at Eridu AI, you will lead the IC Verification team in Bengaluru, shaping the future of AI Networking. This role requires a self-driven individual with a passion for solving real-world problems and a desire to drive innovation in AI networking. Responsibilities: - Manage and lead the Bengaluru team of ASIC verification engineers, ensuring a collaborative work environment and effective communication across different locations. - Provide technical expertise in ASIC verification, ensuring compliance with industry standards and project specifications. - Conduct gate-level simulations, including timing and power analysis, to validate ASIC designs before tape-out. - Oversee RTL coverage analysis and provide feedback to enhance test suite thoroughness. - Collaborate with Firmware teams to ensure seamless integration between hardware and firmware components. - Mentor team members, identify training needs, and manage team augmentation in different locations. Qualifications: - ME/BE in Electrical Engineering, Computer Engineering, or related field. - Minimum 12 years of experience in ASIC verification, particularly in networking ASIC design. - Expertise in Hardware Verification Methodology, System Verilog, UVM, gate/timing/power simulations, and test-plan documentation. - Prior experience with Ethernet, UCIe, and PCIe protocols, high-speed SerDes, and global team management. - Excellent communication skills to lead and coordinate a diverse team effectively. Join Eridu AI to be part of a team that is revolutionizing AI infrastructure and shaping the future of AI networking. Your work will directly impact the next generation of AI networking solutions, pushing the boundaries of AI performance. The starting base salary will be determined based on skills, experience, qualifications, market trends, and comparable roles in the industry. Visit eridu.ai to learn more about our company and team.,

As a RTL Design Engineer for DDR Memory Controller IP development team at Cadence, your primary responsibility will be to design and support the RTL of the DDR Memory Controller solution. You will be working with the existing RTL, adding new features, and ensuring that all leading DDR memory protocols, including DDR4/LPDDR4, are supported. Your tasks will also involve ensuring customer configurations are clean as part of verification regressions, providing customer support, and ensuring the design meets LINT and CDC design guidelines. To qualify for this position, you should have a BE/B.Tech/ME/M.Tech degree in Electrical/Electronics/VLSI and proven experience as a design and verification engineer, with a significant focus on RTL design and development. Proficiency in RTL Design using Verilog is essential, and familiarity with System Verilog and experience in using/debugging in a UVM based environment are required. AXI3/4 experience is preferred, and prior experience with DDR Memory controller and protocols is highly advantageous. Additionally, having prior experience in RTL design and implementation of complex protocols and working in IP development teams will be beneficial for this role. At Cadence, we are committed to making an impact on the world of technology by hiring and developing leaders and innovators like you. Join us in our mission to solve challenges that others can't and be part of a team that is dedicated to work that matters.,

As a Principal Product Engineer at Cadence, you will be a part of a team that is at the forefront of electronic design, leveraging over 30 years of computational software expertise to transform design concepts into reality. You will have the opportunity to work with the world's most innovative companies, contributing to the development of extraordinary electronic products across various dynamic market applications such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health sectors. Cadence offers a stimulating work environment that fosters creativity, innovation, and impact. Our employee-friendly policies prioritize the physical and mental well-being of our workforce, support career development, provide continuous learning opportunities, and recognize and celebrate individual and collective successes. Our unique "One Cadence - One Team" culture emphasizes collaboration both within and across teams to ensure customer success. In this role, you will work with a diverse and passionate team of individuals who are dedicated to exceeding customer expectations and making a difference every day. Cadence provides numerous avenues for personal and professional growth, regardless of where you are in your career journey. To excel in this position, you should have a solid understanding of Hardware Description Languages (HDL) such as Verilog, System Verilog, and VHDL, along with experience in logic synthesis tools. Proficiency in timing concepts, SDCs, PPA push and analysis, 1801/UPF concepts, awareness of P&R flows, and power analysis and optimization would be advantageous. The ideal candidate should hold a BE/BTech/ME/MS/MTech degree or equivalent qualification. If you are looking to be part of a team that is committed to solving challenging problems and making a meaningful impact, Cadence is the place for you. Join us in our mission to tackle what others cannot.,

You will be responsible for developing the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Additionally, you will participate in defining the architecture and microarchitecture features of the block being designed. You will apply various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals, as well as design integrity for physical implementation. It will be your responsibility to review the verification plan and implementation to ensure design features are verified correctly. You will also resolve and implement corrective measures for failing RTL tests to ensure the correctness of features. Providing support to SoC customers to ensure high-quality integration and verification of the IP block will also be a part of your role. Furthermore, you will drive quality assurance compliance for a smooth IP SoC handoff. Qualifications: - A Master of Science (or a Master of Technology) degree in Electrical Engineering with more than six years of relevant industry experience, or a Bachelor of Science (Bachelor of Technology) degree in Electrical Engineering with more than eight years of relevant industry experience. - Expertise in microarchitecture, design, development, and integration of design blocks (IP) for system-on-chip (SoC) components. - Knowledge of power management is preferred, and experience with formal apps would be beneficial. - Expertise in Verilog and System Verilog-based logic design. - Experience in synthesis flow and timing closure, CDC, FEV. Knowledge of Python, Perl is a must. - Knowledge of considerations for performance, power, and cost optimization is desirable. - Knowledge of formal property verification using Jasper is preferred. - Demonstrate excellent self-motivation, communication, strong problem-solving, and teamwork skills. - Ability to set aggressive goals and meet/beat commitments. - Flexible enough to work in a dynamic environment and multitask seamlessly, with the ability to work independently and in a team. - Knowledge in IPs like I2C, I3C, SPI, UART, etc., is preferred. - Experience in the field of Dfx (ATPG coverage, SCAN insertion, VISA insertion, etc.) will be an added advantage. In this role, you will work within the Client Computing Group (CCG) at Intel, responsible for driving business strategy and product development for Intel's PC products and platforms. The CCG aims to deliver purposeful computing experiences that unlock people's potential, allowing each person to focus, create, and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. This role will be eligible for a hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site. Please note that job posting details such as work model, location, or time type are subject to change. ,

As a SOC Performance Modeling Engineer at AMD, you will be an integral part of the Client Performance Modeling Team based in Hyderabad, India. Your primary responsibility will involve analyzing the architectural performance of notebook and desktop processors through modeling and RTL simulation. By collaborating with SoC, IP & Model architects, you will evaluate and debug CPU/GFX/NPU processor performance and suggest architectural enhancements to drive innovation. To excel in this role, you should possess a deep passion for cutting-edge SoC architecture, digital design, and verification. Your effective communication skills and ability to work seamlessly with architects & engineers across different locations and time zones will be crucial. Strong analytical and problem-solving abilities are essential, coupled with a willingness to learn and tackle challenges head-on. Key responsibilities in this role include developing architectural models, tools, and infrastructure, optimizing performance features, proposing enhancements for next-gen SOCs, conducting trade-off studies for performance, power, and area, evaluating benchmarks for various processors, advancing simulation infrastructure and methodology, and providing technical guidance to the Client SoC team. The ideal candidate would have 3-15 years of industry/academic experience, expertise in computer system simulation and performance evaluation, familiarity with ASIC HW design and verification languages/tools such as Verilog, System Verilog, System C, OVM/OVC, proficiency in programming and scripting languages like C/C++, Perl, Python, and a track record of analyzing system bottlenecks to optimize computing systems for performance. Additionally, detailed microarchitecture knowledge of CPU, GPU, NPU, I/O subsystem, and/or DRAM controller would be advantageous. An academic background in Computer/Electrical Engineering with a Bachelor's or Master's degree is required to qualify for this position at AMD. Explore the AMD benefits at a glance to discover the comprehensive perks offered to our valued employees.,