1850 System Verilog Jobs - Page 8

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum Qualifications Previous experience working on complex high-performance RTL design, preferably on DSP or processor based sub-system. Expert in hardware (RTL) design in Verilog, System Verilog or VHDL. Knowledge of standard on chip bus interface protocols (AXI, APB, AHB) Experience with some of below. Model development (SystemC, or C++) RTL to gates synthesis (Synopsys DCG or Cadence Genus) Design rule and CDC checking (SVA assertions, Spyglass, 0-in) Work on high performance low power RTL design. Scripting languages (PERL, Python, TCL, C, etc.) PRINCIPAL DUTIES AND RESPONSIBILITIES: Develop micro-ar...

Lead and mentor a verification team in Gurugram, driving UVM-based testbench development, protocol validation (PCIe, Ethernet, AXI, etc.), and project execution with strong SystemVerilog expertise and leadership skills. Required Candidate profile Seeking a Verification Lead with 8–16 years’ experience in RTL, System Verilog, UVM, and PCIe, to lead in-office projects for Gurugram location.

About The Role Your Role As a SoC GLS Verification Engineer , you will play a key role in verifying complex SoC designs through Gate-Level Simulation (GLS). You will work closely with design and verification teams to ensure functional correctness, timing accuracy, and overall quality of silicon-ready designs. Your expertise in GLS methodologies and debugging will be critical in delivering high-performance, reliable SoCs. In this role, you will: Perform GLS using Zero Delay , SDF , and Post-Layout GLS (PAGLS) techniques. Debug and resolve issues in gate-level simulations to ensure timing and functional correctness. Develop and maintain SystemVerilog/UVM testbenches for GLS environments. Colla...

About The Role This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; About The Role - Grade Specific Focus on Electrical, Electronics and Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in ...

About The Role : Job TitleVice President LocationDLF Square, Gurgaon Role Description The Sales Specialist works with the Lead Salesperson to meet agreed sales and revenue targets. The Sales Specialist will generate detailed client / product knowledge, market knowledge and cultivate client relationships in order to generate sales opportunities. The Sales Specialist will work to develop deep understanding of the client need / product detail and Banks capabilities with the aim of meeting client satisfaction expectations. The Sales Specialist will be conversant relevant legal, regulatory and Bank policy requirements and operate accordingly. Together with the Lead Salesperson ensure liaison with...

Functional Verification Engineer Job Title: Functional Verification Engineer Experience: 2-5 years Education: B.Tech/M.Tech in ECE/EE Responsibilities: Develop directed/random testcases for verifying functional specs Use UVM-based testbenches for simulation Identify corner cases and achieve high coverage metrics Participate in verification planning and reviews Requirements: Deep understanding of SoC/IP-level functional verification Proficient in UVM, System Verilog, and scripting Familiarity with assertion-based verification (SVA)

RTL Verification Engineer Job Title: RTL Verification Engineer Experience: 0-3 years Education: B.E/B.Tech/M.Tech in ECE or related field Responsibilities: Develop testbenches in System Verilog Write and execute testcases for RTL validation Perform code coverage and functional coverage analysis Debug simulation failures and regressions Requirements: Good knowledge of Verilog/System Verilog Basic understanding of UVM and testbench architecture Experience with simulation tools like VCS or Questa

Develop and maintain formal equivalence checking flows using Synopsys Formality. Collaborate with cross-functional teams to align verification methodology with design goals. Implement and support Formality ECO flows for incremental synthesis. Drive methodology improvements for SoC design verification. Coordinate with internal stakeholders and external vendors to deliver high-quality solutions. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Bachelor’s or Master’s degree in Computer Science, Electronics Engineering, or VLSI Design. 5–8 years of hands-on experience with Synopsys Formality or similar tools (e.g., Cadence Con...

Designation: Technical Support Engineer - VLSI Experience : 0-1 Years Education : B.tech/ BE- or M.Tech VLSI. ECE/ Diploma in Mechatronics/ECE Industry Type: Education / E-Learning / Semiconductor Category: Technical Job Description Responsible for development and support of Projects. Responsible for debugging the source codes in Verilog, SV, and UVM. Responsible for Monitoring the trainee's progress. Will be a point of contact for trainees to query on Technical concepts. Desired Candidate Profile Sound Knowledge on Verilog, SV, Digital ,UVM / Back-end design Good communication skill. Should be good in Digital Electronics. For more details kindly contact 7406043555, fiza@maven-silicon.com

Mixed-Signal Design Engineer Job Title: Mixed-Signal Design Engineer Experience: 2- 6 years Education: M.Tech in Microelectronics/Analog/RF/VLSI Responsibilities: Design and verify mixed-signal IPs (SerDes, ADC/DAC, PHY) Perform behavioral modeling (Verilog-A, System Verilog) Collaborate on AMS verification and top-level integration Work on co-simulation and layout parasitic impact analysis Requirements: Understanding of both analog and digital design flows Familiar with AMS verification tools and SPICE simulations Knowledge of signal integrity and noise isolation

4+ years of experience in System Verilog & UVM. Expertise in any one of the industry standard protocol like PCIe, Ethernet, DDR, USB, UCIe, AXI etc.

Candidates with 1-3 Yrs expertise in SV, UVM, Verilog, DV, RTL design knowledge. Preferred VLSI Diploma course mandatory.

As a Senior ASIC CAD/EDA Engineer in the VLSI/Semiconductor Industry, your role involves deploying and supporting front-end tools, developing scripts for automation, working closely with design, implementation, and verification teams. You will be responsible for: - Deploying and supporting front-end tools like RTL simulators, low power tools, static RTL checkers, and formal verification tools - Developing scripts to automate regression and debug flows, enabling CI/CD - Streamlining compute infrastructure utilization using load distribution tools - Identifying and prioritizing internal user needs and developing capabilities for them - Integrating tools, repos, and compute infrastructure using...

Role Overview: You will be independently executing mid-sized customer projects in the field of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, your responsibility will include owning a task in RTL Design/Module and providing support and guidance to engineers in various areas like Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. Anticipating, diagnosing, and resolving problems by coordinating with cross-functional teams to ensure on-time quality delivery approved by the project manager and client will be crucial. Key Responsibilities: - Automate design tasks flows and write scripts to generate re...

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6....

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC ver...

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / s...

Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test cases including fai...

Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from de...

Roles and Responsibilities: 1. Handling request from vessel or TSI for Adding / amending /removal of PMS routines: Amendment request from vessel is sent to TSIs approval and as technical committee member same will be forwarded to PMS DB (by referring technical manuals, makers manual, makers circular). Activation of calendar-based work order while new job is added. For counter-based work order liaising with vessel and activating the same. on completion making sure amendments are reflecting in shore end as requested and intimating the same to vessel /TSI. 2. On signers briefing: For newly joining officers briefing on Shippalm v3 for all 5 modules provide on daily basis via MS teams and physica...

Compiler development for converting SNORT rule set to state table, Regex look up in conjunction with FPGA based acceleration and result processing C++/C based compiler design and development Strong communication skills to interact with the customer,

Key Responsibilities: Develop, integrate, and validate RTL designs for complex ASIC/SoC projects. Perform lint checks, CDC analysis, and RDC verification using industry-standard tools (Spyglass, Meridian, etc.). Collaborate with design verification teams to ensure functional correctness and quality sign-off. Drive synthesis-friendly RTL coding practices and participate in design reviews. Debug and resolve issues across RTL, lint, CDC, and timing. Work closely with architecture and verification teams for spec-to-RTL implementation . Required Skills & Expertise: 5+ years of experience in ASIC RTL design & verification . Strong hands-on expertise in Lint, CDC, and Meridian tools. Proficiency in...

Role Overview: You have been invited to join Coventine Digital Private Limited as a Senior/Lead Design Verification Engineer in Siruseri, Chennai. In this role, you will work directly with a prominent client, contributing to the development of next-generation chip-level verification environments utilizing System Verilog and UVM methodologies. Key Responsibilities: - Conduct functional verification at both block and chip levels for complex designs. - Develop verification test plans based on detailed design specifications. - Construct UVM-based simulation environments using System Verilog. - Perform coverage analysis to ensure validation completeness. - Implement assertion-based verification f...

As an individual contributor in this role, you will be responsible for executing small to mid-size customer projects in various fields of VLSI Frontend, Backend, or Analog design with minimal supervision. Your key responsibilities will include: - Owning specific tasks related to RTL Design/Module - Providing support to junior engineers in areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff - Analyzing and completing assigned tasks within the defined domain successfully and on-time - Ensuring clean delivery of designs and modules - Meeting functional specifications and design guidelines without deviation - Documenting tasks and work p...