1277 System Verilog Jobs - Page 8

NVIDIA has been redefining computer graphics, PC Gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s motivated by phenomenal technology and outstanding people. Today, we are tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. The HWPM Team at NVIDIA is seeking an excellent ASIC Verification Engineer to drive high-quality, robust verification of system-level IP across unit, subsystem, and SoC levels. This role is ideal for someone passionate about ground-breaking hardware, sophisticated verification methodologies, and crafting the future of computing. Come join the team and see how you can make a lasting impact on the world. What You ll Be Doing: Play a key role in the Hardware Performance Monitor (HWPM) team, helping define and develop system-level RTL and performance measurement methodologies for NVIDIA s industry-leading SoCs and GPUs. Develop comprehensive test plans, implement tests, and apply robust verification strategies to validate microarchitecture and design functionality. Design and implement reusable, scalable testbenches and testbench components using System Verilog and UVM. Collaborate with architects, RTL designers, and software engineers to drive feature completeness, performance visibility, and verification closure. What we need to see: M. Tech. (or equivalent) in VLSI or Electronics Engineering OR B. Tech with 2+ years of experience in a similar domain Hands-on experience in unit and/or system level verification Ability to contribute to testbench development and maintenance, preferably using System Verilog and standard methodologies Proficiency in Python or industry-standard scripting languages for automation and test development Proven debugging fundamentals ability to read waveforms, analyze logs, and isolate issues effectively Familiarity with industry-standard tools such as VCS, Xcelium, Verdi, or similar simulation/debug environments Good understanding of RTL design concepts and experience working with Verilog or SystemVerilog Experience with UVM (Universal Verification Methodology) is a strong plus Clear communication skills and collaborative attitude, with ability to work alongside design, DV, and automation teams Widely considered to be one of the technology world s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. Also, e have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our outstanding engineering teams are growing fast. If you are creative, curious, and motivated with a real passion for technology, we want to hear from you! #LI-Hybrid

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers.Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLLAdditional responsibilities:logic (RTL) design, timing closure, CDC analysis etc.Understand and Design Power efficient logic.Agile project planning and execution.RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Minimum 8+ years of experience in Chip design and development. Understand CPU / GPU / RISC V architectures. Expertise in one of the architecture and design of Core units (Fetch, Decode, arithmetic units -adders, multipliers, L1/L2/L3 cache , Mem , IO ) Understand RISC V core Experience with VLSI Design in VHDL / Verilog

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are also looking for candidates with Strong C/C++background to lead our leading-edge algorithmswithin our EDA solutions to increase our design team’s productivity and chip quality and performance. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Strong interpersonal skills are needed to coordinate deliverables and requirements from several areas within and outside of the organization.There are many opportunities to gain and utilize a deep understanding of future issues and provide input towards decisions affecting system development, logical and physical design as well as sophisticated methodology directions. Individuals who are chosen to become a part of our world class development teams will be helping advance IBM’s leadership in developing the highest performing computers and changing hardware solutions. Do you want to be an IBMerCome THINK with us! Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 4+ years of IT experience Strong C/C++programming skills in a Unix/Linux environment is a must. VLSI knowledge, Knowledge in front end linting tools and checkers and RTL Checkers. Great scripting skills – Perl / Python/Shell Proven problem-solving skills and the ability to work in a team environment are a must Preferred technical and professional experience RTL Lint Checkers , Front end verification flow, VLSI knowledge, VHDL/Verilog, computer architecture

Design and development of processor L2 , L3, Non cacheable units and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. . Required education Master's Degree Preferred education High School Diploma/GED Required technical and professional expertise 8 to 15 years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design,

Your Role and Responsibilities Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic units. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

Your Role and Responsibilities Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic unit. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

As a Formal verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Develop the verification environment and test bench and creating testcases. Develop skills in IBM Formal verification tools and methodologies. Work with design as well as other key stakeholders in resolving/debugging logic design issues and deliver a quality design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5 – 10 years of relevant industry experience Proven experience in Formal/Functional Verification - Demonstrated execution experience of verification of logic blocks verification. Knowledge of formal methodology, Knowledge of HDLs (Verilog, VHDL, SV), Good programming skills in python, processor core u-arch skills Exposure in developing testbench environment, debugging and triaging fails. Good communication skills and be able to work effectively in a global team environment. Drive verification coverage closure, lead verification team. Drive complex scenarios, participate in High level design discussions. Track record in leading teams. Preferred technical and professional experience Writing test plans, building random / exhaustive formal verification environment, functional and coverage analysis and debug. Good understanding of the Server System

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL/Test Pervassive Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. RequirementsMasters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system performance. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -8+ years of relevant experience - At least 1 generation of processor core/cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Role & responsibilities Core Requirements Basic understanding of CMOS and gate level circuit designs Familiarity with SPICE Familiarity with Verilog simulations Good communication skills and ability to work well in a team Preferred Qualities Analytical capability for complex gate level circuit designs Experience in SystemVerilog, PLI coding Experience in UVM Test Bench Experience in DRAM, SRAM or other memory related fields Experience Level 5+ years Preferred candidate profile

As a Sr. Verification Engineer specializing in SOC Verification, you will be a valuable member of the SmartSoC team, contributing your expertise to intricate SOC Verification projects. Your responsibilities will entail the technical execution of SOC Verification projects for complex ARM-based SOCs. This involves tasks such as Test Planning, Environment Architecture, and creating SV-UVM environments to ensure the successful verification of SOC designs. To excel in this role, you should possess 3 to 10 years of experience in Design Verification, coupled with excellent Communication and Presentation Skills. Your proficiency in SOC Verification is crucial, along with your expertise in Verification methodologies such as Coverage Driven Test Planning, Environment Architecting, and Verification Flow. A strong command of System Verilog is essential, as well as familiarity with methodologies like OVM, UVM, VMM, or RVM. Furthermore, your knowledge of protocols, specifically one of SATA, USB, Ethernet, or PCIE, will be highly beneficial. Your willingness and ability to adapt to new methodologies, languages, and protocols are key attributes for success in this role. This position falls under the Job Category of VLSI (Silicon Engineering) and offers opportunities in various locations including Bangalore, Chennai, Hyderabad, Noida in India, Stockholm in Sweden, and Texas in the USA. Join us at SmartSoC and be part of a dynamic team working on cutting-edge SOC Verification projects.,

Increasing digitalization and flexibility of production processes presents outstanding potential. In Digital Industries, you enable customers to unlock their full potential and drive digital transformation with a unique portfolio of automation and digitalization technologies. From hardware to software to services, Siemens has quite a lot to offer. The company blurs the boundaries between industry domains by integrating the virtual and physical, hardware and software, design and manufacturing worlds. With the rapid pace of innovation, digitalization is no longer tomorrow's idea. Siemens takes what the future promises tomorrow and makes it real for customers today. Join Siemens, where your career meets tomorrow. Siemens is looking for Siemens EDA ambassadors. The Veloce Transactor Group, part of Mentor Emulation Division R&D located in Noida, develops transactors (RTL based IPs/VIPs) for various protocol solutions in Networking, Display, Storage, Mobile, Automobile, etc. The Veloce Transactor Library currently supports more than 25 protocol solutions and is growing further. As an individual in this role, you will be responsible for developing transactor (xVIP) solutions for CCIX or PCIe based interconnect technology. Your primary responsibilities will include understanding standard specifications, developing architecture and micro-arch for the design, and writing a synthesized design using Verilog/System Verilog. Required Experience: - We are seeking a graduate with at least 1-5 years of relevant working experience with (BE/BTech/ME/MTech/MS) from a reputed engineering college. - Your experience with protocols such as PCIe, USB, Ethernet, AMBA in Design or Verification is valued. - A good understanding of IP Verification Methodologies, Verification procedures, and practices are a plus. Experience in one or more verification techniques such as simulation, emulation, acceleration, formal, etc., is beneficial. - Expertise in Verilog, SystemVerilog, and SystemC, as well as experience in developing RTL for FPGAs, ASICs, and IPs, will greatly contribute to the quality of Siemens products. - Candidates should be able to build verification test plans and environments, develop test cases, utilize VIPs, and efficiently debug defects identified during verification processes. - Exposure to object-oriented programming languages like C++ is considered an advantage. Experience in scripting languages such as Perl will also be valuable in automating tasks and improving efficiency. Engagement with customers for Deployment and R&D assistance is required. Siemens has a lot to offer, how about you Siemens - where we are always challenging ourselves to build a better future. With some of the most inquisitive minds working across the world, re-imagining the future and doing extraordinary things.,

You are a talented and experienced Micro-architect RTL Engineer who will join a dynamic team. You have a strong background in multiple technologies and exposure to ARM or microprocessor design and networking. With over 10 years of experience, you will design and implement RTL microarchitecture for high-performance processors, optimizing components for efficient execution and low-power consumption. Your collaboration with cross-functional teams will help achieve project goals, including performance analysis and optimization of designs. You will also contribute to verification plans and methodologies, staying updated with industry trends. As a qualified candidate, you hold a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Your extensive experience in RTL design using VHDL, Verilog, or System Verilog, along with a proven track record in microarchitecture design, makes you a valuable asset. Your familiarity with ARM or microprocessor design, networking concepts, and protocols, coupled with proficiency in design and simulation tools, helps you excel in this role. Your problem-solving skills, attention to detail, and communication abilities are essential for success. Preferred qualifications include experience with low-power design techniques, formal verification, and validation methodologies. Knowledge of scripting languages like Python or Perl is beneficial for automation purposes. In return, you will be part of a collaborative and innovative work environment with opportunities for professional growth and development. A competitive salary and benefits package await you as you work on cutting-edge technology projects that have a real impact. If you are interested in this opportunity, please share your updated resume at maruthiprasad.e@eximietas.design. The position is available in Bangalore & Visakhapatnam.,

You are invited to join Lattice Semiconductor as a SoC RTL Design Engineer in Pune, India. Lattice is a global community of engineers, designers, and specialists working in collaboration with sales, marketing, and support teams to develop cutting-edge programmable logic solutions that are revolutionizing the industry. As a SoC RTL Design Engineer at Lattice Semiconductor, you will be part of a dynamic team dedicated to IP design and full chip integration. This role offers ample opportunities to contribute, learn, innovate, and grow within a fast-paced and results-oriented environment. Key responsibilities of this role include working on FPGA projects, RTL design, SoC integration, and ensuring design quality through various quality checks. You will collaborate with architects and micro-architects to define design specifications and drive logic design efforts for key FPGA blocks and full chips. To excel in this role, you will need a BS/MS/PhD in Electronics Engineering, Electrical Engineering, Computer Science, or equivalent, along with at least 5 years of experience in logic design across multiple silicon projects. Expertise in SoC integration, familiarity with FPGA designs, and the ability to work with various teams across different sites and time zones are essential for success in this position. At Lattice, we value our employees as our greatest asset and are committed to providing a comprehensive compensation and benefits program to attract, retain, and celebrate top talent in the industry. If you thrive in a collaborative environment, are a problem-solver, and have a passion for innovation, Lattice Semiconductor may be the perfect fit for you. Join us at Lattice Semiconductor and be part of a team that is dedicated to customer success and driven by a shared commitment to excellence. To learn more about our innovative programmable design solutions, visit www.latticesemi.com and follow us on Twitter, Facebook, and RSS. At Lattice, we embrace diversity and welcome applications from all qualified candidates who can contribute to our dynamic workplace. Feel the energy at Lattice Semiconductor and discover a rewarding career where you can make a real impact in the industry.,

Eximietas Design is looking for an experienced and highly skilled RTL Micro Architect with over 8 years of experience to join the team. In this role, you will be instrumental in defining and implementing the microarchitecture of advanced semiconductor designs. Your responsibilities will include tackling complex RTL design challenges, collaborating with various teams, and contributing to the delivery of high-performance, power-efficient, and innovative solutions. As the RTL Micro Architect, your key responsibilities will involve defining and developing microarchitecture specifications for complex SoC designs, leading RTL design and implementation using Verilog/System Verilog, and collaborating with cross-functional teams to ensure successful project execution. You will also be expected to perform design trade-off analysis, develop design methodologies for efficiency improvement, mentor junior engineers, and participate in design reviews to provide technical leadership. To qualify for this role, you should have at least 5 years of hands-on experience in RTL design and microarchitecture development, strong expertise in using Verilog/System Verilog for RTL design, and proficiency in microarchitecture design for complex SoCs. Experience with low-power design techniques, familiarity with advanced process nodes, and scripting skills in Tcl, Python, or Perl will be advantageous. Additionally, strong problem-solving skills, attention to detail, communication, and leadership skills are essential for this position. In return, Eximietas Design offers you the opportunity to work on cutting-edge semiconductor designs and innovative technologies in a collaborative and inclusive work environment. You can expect a competitive compensation and benefits package along with professional growth and development opportunities. If you are interested in this exciting opportunity, please share your updated resume with us at maruthiprasad.e@eximietas.design. Join us in shaping the future of semiconductor designs!,

Qualcomm India Private Limited is seeking a qualified Hardware Design Engineer with 5-8 years of experience in ASIC IP cores design to join their Engineering Group. In this role, you will be responsible for working independently on peripheral IPs, designing and proposing microarchitecture solutions, guiding and mentoring junior team members, and collaborating with external teams to resolve cross-team dependencies. Additionally, you will be expected to take complete ownership of one or more projects and drive them independently. The ideal candidate should possess a Bachelor's degree in Electrical Engineering (Master's degree preferred) and have a strong knowledge of AMBA protocols such as AXI, AHB, and APB. Experience with SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and Ethernet is desirable. Hands-on experience in Low power design, Multi Clock designs, and Asynchronous interfaces is required. Proficiency in using ASIC development tools like Lint, CDC, Design compiler, and Primetime is necessary. Furthermore, the successful candidate should have a good understanding of constraint development, timing closure, and synthesis concepts. Strong experience in micro architecting RTL design from high-level design specification is essential. Proficiency in System Verilog, Verilog, C/C++, Perl, and Python is a plus. Excellent problem-solving, communication, and teamwork skills are mandatory for this role. The ability to lead a small design team and work with minimal supervision is also required. Minimum qualifications for this position include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 3 years of Hardware Engineering experience. Alternatively, a Master's degree with 2+ years of relevant experience or a PhD with 1+ year of experience will also be considered. As a Hardware Design Engineer at Qualcomm, you will leverage your knowledge and experience to plan, optimize, verify, and test electronic systems. You will collaborate with various teams to implement new requirements and incorporate the latest test solutions to improve yield, test time, and quality. Your responsibilities will also include evaluating and developing manufacturing solutions for leading-edge products, ensuring reliability, and identifying potential design flaws or compatibility issues. This role requires independent work with minimal supervision, providing guidance to team members, and making decisions that may impact work beyond the immediate team. Strong verbal and written communication skills are essential for conveying information effectively. Problem-solving and prioritization skills will be necessary to complete tasks efficiently. If you meet the qualifications and are interested in joining Qualcomm's dynamic team, we encourage you to apply for this exciting opportunity.,

We are hiring 8+ years of hands-on DV experience in System Verilog/UVM.

"> Search Jobs Find Jobs For Where Search Jobs Senior Design Verification Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12213 Remote Eligible No Date Posted 21/07/2025 Alternate Job Titles: Functional Verification Engineer Pre-Silicon Verification Engineer Digital Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and enthusiastic individual with a strong drive to learn and excel in the field of digital verification. You have a keen eye for detail and a deep understanding of digital design and hardware description languages (HDL). With your expertise in functional verification, you are eager to contribute to the pre-silicon verification activities for high-speed interface IPs. You possess excellent problem-solving skills and can work effectively in a collaborative environment. Your proactive approach and strong communication skills enable you to work closely with digital designers to achieve desired coverage and ensure the highest quality of IPs. What You ll Be Doing: Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers. What You ll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating functional verification environments. Who You Are: An excellent communicator who can collaborate effectively with cross-functional teams. A proactive problem solver with a keen eye for detail. An enthusiastic learner with a passion for technology and innovation. A team player who thrives in a collaborative environment. A highly organized individual who can manage multiple tasks and priorities effectively. The Team You ll Be A Part Of: You will be part of a dedicated and innovative team focused on the functional verification of high-speed interface IPs. Our team collaborates closely with digital designers and engineers to ensure the highest quality of IPs. We are committed to continuous learning and development, fostering an environment where creativity and innovation thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

"> Search Jobs Find Jobs For Where Search Jobs Senior Verification Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12303 Remote Eligible No Date Posted 21/07/2025 Alternate Job Titles: Functional Verification Engineer Pre-Silicon Verification Engineer Digital Design Verification Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic and enthusiastic individual with a strong drive to learn and excel in the field of digital verification. You have a keen eye for detail and a deep understanding of digital design and hardware description languages (HDL). With your expertise in functional verification, you are eager to contribute to the pre-silicon verification activities for high-speed interface IPs. You possess excellent problem-solving skills and can work effectively in a collaborative environment. Your proactive approach and strong communication skills enable you to work closely with digital designers to achieve desired coverage and ensure the highest quality of IPs. What You ll Be Doing: Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and functionality of high-speed interface IPs, contributing to the development of cutting-edge technology. Enhancing the reliability and performance of Synopsys products through meticulous verification processes. Driving innovation in the semiconductor industry by verifying complex digital designs. Collaborating with a team of skilled professionals to deliver high-quality IPs that meet industry standards. Improving the efficiency of the verification process through automation and advanced verification methodologies. Contributing to the overall success of Synopsys by ensuring the delivery of robust and reliable IPs to customers. What You ll Need: B.Tech/M.Tech with 3+ years of relevant experience. Understanding of functional verification flow with awareness of verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in scripting and automation using TCL, PERL, or Python. Strong debug and diagnostic skills. Experience in building and updating functional verification environments. Who You Are: An excellent communicator who can collaborate effectively with cross-functional teams. A proactive problem solver with a keen eye for detail. An enthusiastic learner with a passion for technology and innovation. A team player who thrives in a collaborative environment. A highly organized individual who can manage multiple tasks and priorities effectively. The Team You ll Be A Part Of: You will be part of a dedicated and innovative team focused on the functional verification of high-speed interface IPs. Our team collaborates closely with digital designers and engineers to ensure the highest quality of IPs. We are committed to continuous learning and development, fostering an environment where creativity and innovation thrive. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

Qualcomm India Private Limited is seeking a skilled ASIC IP cores design engineer to join their Hardware Engineering team. In this role, you will be responsible for designing and working independently on peripheral IPs, developing design and microarchitecture solutions, guiding and mentoring junior team members, and collaborating with external teams to drive and resolve cross-team dependencies. You will take complete ownership of one or more projects and drive them independently, with the ability to provide schedule estimates and potentially manage people. To be successful in this role, you should have 5-8 years of work experience in ASIC IP cores design and hold a Bachelor's degree in Electrical Engineering, with a preference for a Master's degree. Knowledge of AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking/reset/debug architecture and peripherals like USB, PCIE, and Ethernet, is preferred. Experience in low power design, multi-clock designs, and asynchronous interface is required. You should also have hands-on experience with ASIC development tools like Lint, CDC, Design compiler, and Primetime. Additionally, you should possess strong problem-solving skills, excellent communication abilities, and be a team player. Self-driven individuals who can work with minimal supervision and have experience in System Verilog, Verilog, C/C++, Perl, and Python are preferred. The ability to lead a small design team is also a plus. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application and hiring process. If you require accommodation, you can contact Qualcomm for assistance. It is important to note that Qualcomm expects all employees to adhere to company policies and procedures, including those related to the protection of confidential information. If you are a proactive and experienced ASIC IP cores design engineer looking to work in a challenging and collaborative environment, this position at Qualcomm India Private Limited may be the right fit for you.,

Qualcomm India Private Limited is seeking a talented individual to join our Engineering Group, specifically focusing on Hardware Engineering. In this role, you will be responsible for developing micro-architecture and RTL design for Cores related to security, with a primary focus on block level design. Your responsibilities will also include enabling software teams to utilize hardware blocks effectively, as well as running ASIC development tools such as Lint and CDC. Additionally, you will be expected to report progress status and communicate effectively against set expectations. To be considered for this position, you must hold a Bachelor's degree in Engineering, Information Systems, Computer Science, or a related field, along with a minimum of 5 years of Hardware Engineering experience. Preferred qualifications include 5 to 10 years of work experience in ASIC/SoC Design, proficiency in RTL design using Verilog/System Verilog, and knowledge of cryptography concepts such as public/private key, hash functions, and encryption algorithms. Experience in Root of Trust and HW crypto accelerators, defining HW/FW interfaces, Linting, CDC, and LEC will be advantageous. Proficiency in database management flows using tools like Clearcase/Clearquest, as well as programming skills in Verilog, C/C++, Python, and Perl are highly desirable. Excellent oral and written communication skills, along with a proactive and collaborative approach to work, will also be key to success in this role. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please reach out to disability-accommodations@qualcomm.com. It is essential that all employees adhere to applicable policies and procedures, particularly those concerning the protection of confidential information. Please note that Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. If you have any inquiries about this role, please contact Qualcomm Careers directly.,

Job Requirements Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills. Work Experience Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills.

Position – Design Verification Location - Bangalore / Hyderabad / Pune / Chennai / Kochi Experience – 7 - 17 Years SV/UVM Test Bentch Developement Any Protocols: (PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR

We are looking for experienced FPGA Verification Engineer. As a FPGA Verification Engineer, you will work for a high complexity DWDM equipment for LH/ULH applications. You will work in close collaboration with multi location cross-functional R & D teams. Our work includes everything from product concept to finished product - a process that spans over the entire development cycle. The team takes full responsibility for delivery on time with the right quality. As an FPGA Verification engineer, you will be responsible for designing verification plan, developing environment/testbench, creating test scenarios for running simulations, coverage analysis and lab support during board bring up to ensure first time right quality of Infinera product. Candidate should be capable of handling projects independently and strong will to drive for solutions. Education Necessary: Candidates must have a bachelors degree or higher in EE with very good academics. Roles & Responsibilities: Must have 10 years of experience in developing System Verilog UVM based test environments, developing and implementing test plans at block, sub-chip and chip levels. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools. Exposure to UVM (or similar) verification methodologies is required. Familiarity with HDLs such as Verilog and scripting languages such as perl is highly desired. Working knowledge of RTL design is preferred. Should be conversant with technologies like, Ethernet, PCIe etc. Knowledge of telecom protocol is preferred. Structured and thorough with analytical and troubleshooting skills. Good written and oral communication skills are required. Flexible, innovative, self-driven and willing to take own initiatives. Highly motivated team player. We offer: A high pace in development of new products. Tight cooperation with other disciplines. Short product development cycles, Real results of your work, you will see how it affects our products and sales. International possibilities of development and internal advancement. Social and wellness activities and clubs. A friendly and helpful atmosphere. Highly competent and motivated colleagues.

About The Role JD Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Works in the area of Software Engineering, which encompasses the development, maintenance and optimization of software solutions/applications.1. Applies scientific methods to analyse and solve software engineering problems.2. He/she is responsible for the development and application of software engineering practice and knowledge, in research, design, development and maintenance.3. His/her work requires the exercise of original thought and judgement and the ability to supervise the technical and administrative work of other software engineers.4. The software engineer builds skills and expertise of his/her software engineering discipline to reach standard software engineer skills expectations for the applicable role, as defined in Professional Communities.5. The software engineer collaborates and acts as team player with other software engineers and stakeholders. - Grade Specific JD Must have skills. Payment Domain Expertise, MUST - Knowledge on MT and MX Message, Basics of SQL, and Java Specific skillset on MTS and UPF knowledge. Payment domain expertise, knowledge on MT and MX messages Skills (competencies) Verbal Communication

We are now looking to hire strong performance verification engineers with a sharp understanding of CPU and memory architecture. NVIDIA makes some of the fastest CPUs in the world and is solving problems, with its vast arsenal of CPUs, GPUs and SW, in areas such as High-performance computing, Automated driving, Medical imaging and much more! We are seeking highly motivated engineers to join this dynamic and innovative team that owns performance alignment of CPUs and CPU fabrics made by NVIDIA! Do you want to be part of the team that explores and defines the next generation of CPUs What will you be doing: Responsibilities will include development of test plans and strategies, develop simulation environments, system bring-up, validation, and automation to deliver best-in-class CPUs. Develop and maintain CPU simulator infrastructure, hardware CPU test and performance infrastructure. Analyze and validate CPU and fabric performance, helping to understand current, and guide the development of future CPU products. Definition and development of tool chain and workflows that enables the full system performance alignment. Silicon based competitive analysis of NVIDIA CPUs. What we need to see: Masters or Bachelors degree in EE/CS or equivalent experience 5+ years of experience preferably in the areas of CPU / SOC Performance Verification and Analysis Strong understanding of computer system architecture and operating system fundamentals. Hands-on experience with HDLs such as Verilog / System Verilog. Knowledge of verification methodologies and tools for IP and SoC level verification. Experience with System Verilog, C/C++, Python languages and relevant frameworks. Background with debug on Silicon. Ways to stand out from the crowd: Detailed knowledge of the ARM and/or x-86 architecture. Prior experience with performance analysis of CPUs. Experience with analysis and characterization of CPU workloads. #LI-Hybrid