Verification Lead

As a Lead Verification Engineer with over 7 years of experience, you will be an integral part of a geographically distributed verification team working on next-generation ASIC and FPGAs. Your responsibilities will include developing testplans, implementing testbenches, creating testcases, and ensuring functional coverage closure. Additionally, you will handle regression testing, contribute to verification infrastructure development, and develop both directed and random verification tests. In this role, you will be expected to debug test failures, identify root causes, and collaborate with RTL and firmware engineers to resolve design defects and test issues. You will also review functional and code coverage metrics, modify or add tests, and constrain random tests to meet coverage requirements. Furthermore, you will collaborate closely with design, software, and architecture teams to verify the design under test. The preferred experience for this role includes proficiency in IP-level FPGA and ASIC verification, knowledge of protocols such as PCIe, CXL, or other IO protocols, and proficiency in Verilog/SystemVerilog and scripting languages like Perl or Python. Hands-on experience with SystemVerilog and UVM is mandatory, along with experience in developing UVM-based verification testbenches, processes, and flows. A solid understanding of design flow, verification methodology, and general computational logic design and verification is also essential. About the Company: ACL Digital, a leader in digital engineering and transformation and part of the ALTEN Group, empowers organizations to thrive in an AI-first world. With expertise spanning the entire technology stack and seamlessly integrating AI and data-driven solutions from Chip to cloud, ACL Digital offers a strategic advantage in navigating the complexities of digital transformation. Join us at ACL Digital and be a part of shaping the future as our trusted partner.,