28 Systemc Jobs - Page 2

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: General Summary: Qualcomm is the world's leading developer of next generation of always on Display technologies and is committed to building a world-class organization that will lead the industry. Be part of the team developing next generation Display subsystems and Display peripherals. The ASIC Systems Architect is responsible for system architecture definition activities supporting a sophisticated multimedia Low Power Display subsystem catering to various market segments like mobile, XR, compute, IOT, Wearables and automotive products. Candidates will be responsible for all aspects of the ASIC hardware architecture definition/validation including the following: Owning end to end system architecture Capturing detailed technology requirements working closely with product, hardware and software engineering teams for deriving subsystem hardware specification. Engage with all stakeholders and collaborate with cross functional teams to define robust architecture Defining architecture validation plans and reviewing development results Optimization and debug via modelling, system simulation and testing across key criteria including power and performance. Collaborating, reviewing and enabling design and system teams to execute independently from the specifications Engage and provide support from Concept to Commercialization, Post-silicon commercialization support and customer engineering documentation Defining and patenting novel architectures that drive industry leadership. Job Function: Oversees hardware architecture for ASIC systems development for a variety of products. Determines architecture design, and validation via system simulation. Defines module interfaces/formats for simulation. Ability to analyze and solve complex problems through various mechanisms. Ability to optimize architecture for Area, Performance and power efficiency. Evaluates all aspects of the HW architecture flow from high-level development to validation and review. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Uses System tools, such as, MathWorks MATLAB, SIMULINK, VISIO and other toolboxes. Uses language such as HDL, C/C++, System C, Perl, Python. Provides technical expertise for next generation initiatives. Leverages experience in image processing, SoC hardware and computer architecture concepts to develop proposals to address system Display requirements using processor, memory, bus and low-power design techniques. Uses expertise in low-power design methodology, optimization and validation using various CAD tools and design techniques to optimize system power. Leverages experience in digital system performance analysis and systems modelling to ensure performance goals met. Leverages Verilog/VHDL and digital hardware design tools such as Synopsys/Cadence/Mentor ASIC design and simulation tool sets, power analysis and simulation, scripting languages (Python, Perl, TCL, C, etc.) to optimize system. Effectively utilizes advanced problem solving and ASIC engineering practices to resolve complex architecture, design, or verification problems. Writes technical documentation and provides technical expertise for design or project reviews and project meetings. Acts as a tech lead on small to large projects and owns team deliverables of the project. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. Minimum Qualifications: Bachelor's degree in, Electronics/Computer Science Engineering, or related field and 7+ years of ASIC design, verification, or related work experience. OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, or related work experience. OR PhD in Science, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: QCT's Bangalore Wireless R&D HW team is looking out for experienced Wireless Modem HW model developers to work on Qualcomm"™s best in class chipsets in modem WWAN IPs Roles and Responsibilities You will be contributing to flagship modem core IP development covering 5G(NR) & 4G (LTE) technologies. You will be part of team defining and developing next generation multi-mode 5G modems. You will be working on development and verification of HW models of modem core IP. The models are developed on C++/SystemC platform and used as golden reference for RTL verification and pre Silicon FW development ( virtual prototyping). The candidate must be well versed with C++ and should have good exposure to SystemC and/or System Verilog and/or Matlab. The candidate must have ability to understand HW micro-architecture & its modeling abstraction. Working knowledge of physical layer of wireless technologies like NR,LTE , WLAN, Bluetooth is highly desired. Expertise on digital signal processing and working experience on HW modeling and/or RTL design/ verification of IP are preferred. Candidates with SW/FW background on wireless IP can also apply. Candidates with strong technical knowhow on non-wireless DSP based HW IPs ( with Design / Verification/ Modeling skills) will also be considered. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 5-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Skillset/Experience: 5-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.