Signoff and Design Methodology Engineer, Silicon Google

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a candidate for this position, you should hold a Bachelor's degree in Computer Science, IT, a related field, or possess equivalent practical experience. Additionally, you should have at least 5 years of experience in static timing analysis, synthesis, physical design, and automation. It is crucial that you have expertise in physical design tool automation, including synthesis, P&R, and sign-off tools. In addition to the minimum qualifications, preferred qualifications for this role include experience in extracting design parameters, Quality of Results metrics, and analyzing data trends. You should also have knowledge of timing constraints, convergence, and signoff processes, as well as familiarity with parasitic extraction tools and flow. Proficiency in Register-Transfer Level (RTL) languages such as Verilog/SystemVerilog is required, along with a strong understanding of Static Timing Analysis (STA), Electromigration and IR Drop (EMIR), and PDV signoff methodologies. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a key role in innovating products that are beloved by millions worldwide. By leveraging your expertise, you will help shape the next generation of hardware experiences that deliver unparalleled performance, efficiency, and integration. In this role, your responsibilities will include driving sign-off timing methodologies for mobile System on a chip (SoCs) to optimize Power Performance Area (PPA) and yield. You will analyze power performance area trade-offs across various methodologies and technologies, as well as work on prototyping subsystems to deliver optimized PPA recipes. Collaboration with cross-functional teams including architecture, Internet Protocols (IPs), design, power, and sign-off methodology is essential. Furthermore, you will engage with foundry partners to enhance signoff methodology for improved convergence and yield.,

Posted 5 days ago

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Senior Digital Implementation Engineer Analog Devices

2.0 - 10.0 years

2 - 10 Lacs

Bengaluru, Karnataka, India

On-site

STA flow setup, convergence, reviews Timing constraint development, analysis, validation and debug Timing, Noise, DRC (transition, capacitance) signoff for multi-mode, multi-corner STA flow optimization Work ondesign automation using TCL/Perl/Python Position Requirements: BTech/MTech degree in Electrical/Electronics with 2-10 years of experience Hands on experience with the STA and Signoff of complex high speed SoC designs in cutting edge process technologies (16nm and below). Ability to develop complex timing constraints by working with designers. Should have experience in IP/subsystem/full-chip timing constraints Knowledge of timing commands and constructs supported across synthesis, STA and PD tools Analysis skills to root cause of timing violations issues and suggest solutions across various stages of design Implementation Strong expertise in Timing ECOs driven by tool and manual ECO techniques for timing closure Sound understanding of Scan/DFT modes and timing Familiar with digital flow design aspects RTL to GDS Proficiency in tcl/perl/python scripts and automation on timing analysis tools Innovate on the flows to resolve timing or DRC issues Good understanding on device/interconnect and circuit aspect of the complex UDSM technologies is an added advantage. Good communication skills in cross-collaborative environment

Posted 4 weeks ago

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