130 Signal Integrity Jobs - Page 6

Leading the development of next-generation DDR/HBM/UCIe IP. Providing guidance and mentorship to team members, ensuring project schedules are met and problems are resolved efficiently. Acting as a project leader, contributing to complex aspects of IP development. Developing and maintaining project schedules, collaborating with cross-functional teams. Designing and verifying CMOS circuits and layouts. Implementing analog mixed-signal simulation strategies and ensuring signal integrity. The Impact You Will Have: Driving the development of cutting-edge IP that powers the future of technology. Enhancing the capabilities of SoCs, enabling faster integration and reduced risk for customers. Contributing to the success of Synopsys by delivering high-quality IP on time. Leading a team of talented engineers, fostering innovation and excellence. Ensuring the highest standards of product quality and efficiency. Playing a key role in the Era of Smart Everything, from AI to IoT. What You ll Need: BTech/MTech degree in a relevant field. 8+ years of experience in analog design. Knowledge of CMOS processes and deep submicron process technologies. Proficiency in CMOS circuit design and layout methodology. Familiarity with analog mixed-signal simulation strategies. Understanding of JEDEC requirements for DDR interfaces and standards. Strong project management and leadership skills. Excellent written and verbal communication skills. Who You Are: A natural leader with the ability to inspire and guide a team. An excellent problem solver with a keen analytical mind. A collaborative team player who thrives in a cross-functional environment. A detail-oriented individual with a commitment to quality and efficiency. A proactive communicator who can convey complex technical information clearly.

Design and develop analog/mixed-signal blocks for PCIe 6 and PCIe 7 PHY designs. Ensure designs meet PCIe protocol standards, optimizing for performance, power, and area targets. Support the porting of PHY designs to different technology nodes, maintaining signal integrity and performance. Collaborate with cross-functional teams to integrate analog circuits into larger SerDes PHY systems. Implement verification strategies for high-speed analog/mixed-signal circuits using advanced simulation tools. Work closely with physical layout teams to minimize parasitics, device stress, and process variation impacts. Analyze simulation and measurement data for design validation and compliance with PCIe standards. Provide technical guidance to junior engineers in analog/mixed-signal design methods. Document design features, specifications, and test plans for future reference. Work with the characterization team to validate the electrical performance of circuits in silicon. The Impact You Will Have: Drive the development of cutting-edge PCIe 6 and PCIe 7 PHY designs, pushing the boundaries of high-speed analog and mixed-signal circuits. Ensure that Synopsys designs meet the highest standards of performance, power efficiency, and area optimization. Enhance the reliability and integrity of our analog circuits as they are ported to new technology nodes. Foster innovation through collaboration with diverse teams, integrating leading-edge analog circuits into sophisticated SerDes PHY systems. Contribute to the verification and validation of high-speed circuits, ensuring compliance with stringent PCIe standards. Mentor and guide junior engineers, nurturing the next generation of top-tier analog designers. What You ll Need: PhD with 3+ years, or MTech/MS with 8+ years of experience in analog/mixed-signal circuit design, with experience in high-speed interfaces such as PCIe or SerDes PHY designs. Strong experience in transistor-level design of high-speed analog building blocks, such as LDOs, Bandgap references, ADC/DAC, PLLs, DLLs. Experience in high-speed SerDes AFE (Analog Front-End) development, including CTLE and CDR design. Experience designing high-speed SerDes transmitters, with knowledge of equalization techniques (e.g., DFE, FIR filters, TX pre-emphasis). Understanding of jitter budgeting analysis, including sources of jitter and strategies for minimizing its impact. Strong knowledge of CMOS technologies, including finFET and GAA processes. Good understanding of the PCIe protocol, signal integrity requirements, and high-speed clocking. Ability to provide input on layout design to minimize the effects of parasitics and process variations. Who You Are: Detail-oriented with a passion for innovation and excellence. Proactive and able to work independently with limited supervision. Strong communicator capable of effectively collaborating with cross-functional teams. Mentor and leader, eager to share knowledge and help develop junior engineers. Results-driven with a focus on delivering high-quality, reliable designs

Developing next-generation high-speed memory interface PHY IPs (DDR/HBM/UCIe) Executing projects in advanced technologies with a focus on analytical and problem-solving skills Designing high-speed IOs for memory interface PHY IP in CMOS/FinFET/GAA Collaborating with cross-functional teams globally to achieve project goals Ensuring product quality and efficiency in all design tasks Staying updated with the latest industry standards and technological advancements The Impact You Will Have: Driving the development of innovative high-speed memory interface PHY IPs Contributing to the integration of advanced capabilities in SoCs Enhancing the performance, power efficiency, and size optimization of target applications Reducing risk and accelerating time-to-market for differentiated products Collaborating with global teams to deliver high-quality products Setting industry benchmarks for advanced analog design technologies What You ll Need: BTech/MTech degree in a relevant field 3+ years of experience in analog design fundamentals and device physics Proficiency in high-speed IO designs in advanced technologies Experience with ESD and reliability concepts Knowledge of JEDEC requirements for memory interfaces and standards Familiarity with signal integrity and/or power integrity is a plus Who You Are: An analytical thinker with strong problem-solving skills A collaborative team player with excellent communication and interpersonal skills Detail-oriented and capable of executing tasks with high precision and efficiency Adaptable and eager to learn new technologies and industry standards Passionate about innovation and technological advancement

Leading the development of next-generation high-speed memory interface IPs (DDR/HBM/UCIe). Driving projects in new technologies with a focus on analytical and problem-solving skills. Acting as a technical mentor to ensure schedules and product quality are met. Developing and maintaining project schedules, working in cross-functional settings. Demonstrating proficiency in design concepts and methodologies. Taking on people management responsibilities, guiding and developing your team. The Impact You Will Have: Contributing to the development of cutting-edge memory interface PHY IPs that drive technological advancements. Ensuring high-quality product development through effective leadership and technical expertise. Mentoring and guiding your team to achieve their full potential and meet project goals. Collaborating with cross-functional teams to drive innovation and efficiency. Maintaining Synopsys leadership position in the semiconductor industry by delivering top-notch IPs. Shaping the future of technology through continuous innovation and excellence. What You ll Need: Bachelor s or Master s degree in Electrical Engineering or related field. 10+ years of experience in analog/mixed signal design. Knowledge of deep submicron process technologies - CMOS/FinFET/GAA. In-depth understanding of JEDEC requirements for memory interfaces and standards. Familiarity with ESD concepts and signal integrity/power integrity is a plus. Proven ability to lead projects and deliver high-quality products efficiently. Excellent written and verbal communication skills. Who You Are: A visionary leader with a passion for analog design and innovation. Analytical and detail-oriented with strong problem-solving skills. An effective communicator and mentor, capable of guiding and developing your team. Proactive and adaptable, able to thrive in cross-functional settings. Committed to delivering high-quality products and driving technological advancements.

Job Overview TE Connectivity s RD/Product Development Engineering Teams conceive original ideas for new products, introduce them into practice. PCB engineer is scalable to contribute individually. He/she is responsible for delivering the project from schematic scratch till the board get fabricated. Stackup analysis, routing strategy, placement feasibility is more important. RD engineer should familiarize in manufacturing process and the different soldering process, IPC standards for SMT PTH library footprint creation. Responsible for all the documentation related to the board design and fabrication data. Typical fields of expertise include Analysing different dielectric materials, knowledge on high-speed design constraint, electrical, software, automation systems, data packaging, testing and measurement, and manufacturing of electrical, mechanical and electronic components, products, and their integration into systems. Responsibilities: TE Connectivity is seeking an experienced candidate for high speed printed circuit board design. The candidate is expected to interface with US and China based engineering teams for input and independently work on printed circuit board layout while also providing guidance and direction to local designers. The position requires that the candidate be able to utilize generalized engineering direction to create detailed custom designs. The candidate will be responsible for ensuring the accuracy and functionality of the end design and be able to take ownership of various aspects of the PCB design. Programs may additionally include pre-layout analysis and coordination of global vendors for prototype fabrication and assembly. Candidate Desired Profile: Candidate should have excellent verbal communication skills, a high attention to detail, be highly motivated, a quick learner, and be able to work independently. Understanding of printed circuit board design, manufacturing, and assembly is required. Experience with printed circuit board design is required. Experience in a senior technical or leadership role is required. Must be able to deliver the board design from scratch schematic to gerber release for manufacturing. Very good exposure in design software - Altium, Allegro, AutoCAD is must. Previous work experience in high-speed board designs will be highly preferred. Altium/Allegro tool scripting knowledge will be an added advantage for this role. Able to address supplier Engineering Queries. Familiarity with the following a plus: CAM350 High speed and/or RF circuits Signal integrity analysis Connectors and cable assemblies PCB manufacturing tolerances and cost drivers PDMLink process ECR/ECN release process Competencies Values: Integrity, Accountability, Inclusion, Innovation, Teamwork ABOUT TE CONNECTIVITY TE Connectivity is a global industrial technology leader creating a safer, sustainable, productive, and connected future. Our broad range of connectivity and sensor solutions enable the distribution of power, signal and data to advance next-generation transportation, renewable energy, automated factories, data centers, medical technology and more. With more than 85, 000 employees, including 8, 000 engineers, working alongside customers in approximately 140 countries. TE ensures that EVERY CONNECTION COUNTS. Learn more at www. te. com and on LinkedIn , Facebook , WeChat, Instagram and X (formerly Twitter). WHAT TE CONNECTIVITY OFFERS: We are pleased to offer you an exciting total package that can also be flexibly adapted to changing life situations - the well-being of our employees is our top priority! Competitive Salary Package Performance-Based Bonus Plans Health and Wellness Incentives Employee Stock Purchase Program Community Outreach Programs / Charity Events Employee Resource Group Across our global sites and business units, we put together packages of benefits that are either supported by TE itself or provided by external service providers. In principle, the benefits offered can vary from site to site. Location: