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Senior Technical Lead - Design Optimization - FPGAs

Senior Technical Lead - Design Optimization - FPGAs

Thales

6 - 9 years

14 - 19 Lacs

Bengaluru

Posted:1 month ago| Platform:

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Skills Required

Computer science Senior Technical Lead Architecture Aerospace EDA tools Verilog Programming UVM Operations FPGA design

Work Mode

Work from Office

Job Type

Full Time

Job Description

In fast changing markets, customers worldwide rely on Thales. Thales is a business where brilliant people from all over the world come together to share ideas and inspire each other. In aerospace, transportation, defence, security and space, our architects design innovative solutions that make our tomorrows possible. Senior Technical Lead - Design Optimization for FPGAs Essential Specifications: Masters / PhD in Electrical Engineering, Computer Science, or a related field with at least 10 years of experience on FPGA based designs, design optimizations and problem solving. Strong understanding of digital logic fundamentals and computer architecture. Proficiency in FPGA programming techniques. Experience with timing analysis and optimization for FPGA designs. Excellent skills in Verilog programming language. Experience using Vivado or Questa Sim EDA tools. Desirable Specifications: Knowledge of RISC-V architecture. Effective presentation skills to communicate complex ideas. Familiarity with verification techniques using UVM. Responsibilities: Work on a variety of design optimization problems for FPGA-based systems. Collaborate with the team to develop innovative solutions for performance improvement, power optimization, and area reduction. Implement designs using FPGA programming languages like Verilog. Conduct timing analysis and optimize designs to meet performance requirements. Utilize Vivado or Questa Sim EDA tools for design and validation. Stay informed about the latest advancements in FPGA design optimization. Document research findings and project progress accurately. Participate in team meetings, providing valuable insights and suggestions.

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Senior Technical Lead - Design Optimization - FPGAs