Senior Manager, Compact Modeling

Job Description

As a Senior Manager for the Compact Modeling team, you will lead a high-impact team responsible for the development and delivery of compact models that enable next-generation NAND and DRAM technologies. A key part of this role is to foster a culture of technical excellence, collaboration, and continuous learning. You will be expected to mentor and grow technical talent, promote best practices, and create an environment where engineers are empowe'red to innovate and deliver high-quality modeling solutions. This position requires deep technical expertise, cross-functional collaboration, and a strong focus on model accuracy, predictability, and integration into design workflows. Key Responsibilities: Lead a team of engineers in the development, validation, and delivery of compact models across CMOS, interconnect, array, and reliability domains. Own and guide the complete model development lifecycle, including extraction, extrapolation, verification, and documentation. Collaborate closely with CAD, Process Integration, Design Engineering, Product Engineering, and Quality Assurance to ensure models meet performance and design enablement goals. Oversee the design and verification of test structures to support robust model development. Analyze DC and AC device data and direct advanced characterization efforts as needed to support model accuracy. Communicate model performance metrics and predictive insights to global design teams and technical leadership. Drive methodology innovation and continuous improvement in modeling workflows and tool integration. Mentor and develop technical talent, fostering a team culture centered on ownership, collaboration, and technical growth. This position will be based out of Microns Hyderabad site. Qualifications : masters or PhD in Electrical Engineering, Physics, or a related field. 15+ years of relevant experience in the semiconductor industry, with a strong focus on compact modeling. Proven experience in: Compact model development using tools such as BSIMPro+, IC-CAP, MBP, or equivalent. Model verification and validation through circuit simulation and data correlation. Test structure definition and validation. Delivering compact modeling collaterals as part of PDKs or design enablement flows. Strong understanding of CMOS device physics and modeling principles. Hands-on experience with wafer-level device characterization. Familiarity with PDK development, circuit simulators, and design environments. Demonstrated ability to mentor or manage technical teams. Experience in analog or memory circuit design is a plus.