Rtl Designer

Role & responsibilities

Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com

call me :7995220108.

Client Name: Proxelera

Position Name :SoC RTL Integration Engineer

Position type: Permanent

Total Exp: 6-8 years

HBTS Budget: Open

Notice Period: Immediate to 30days

Work Location: Bangalore

Job Description Must have: ead complex SoC integration efforts, including the development of top-level architecture and interconnect fabric *Design and implement critical integration components such as clock/power distribution networks, reset controllers, and system-level arbitration *Resolve sophisticated interface compatibility issues between IP blocks from various sources *Develop and maintain comprehensive integration verification strategies *Collaborate with IP teams to ensure seamless integration of all subsystems *Perform thorough clock domain crossing (CDC) and power domain crossing (PDC) analysis *Drive timing closure at the integration level in coordination with physical design teams *Implement and optimize system-level power management schemes *Lead design reviews and provide technical guidance to junior integration engineers *Develop technical specifications for SoC-level integration requirements Required Technical Skills:- *7+ years of RTL design experience with 4+ years focused on SoC integration *Expert knowledge of industry-standard bus protocols (AXI, AHB, APB, etc.) *Proven experience with large-scale integration challenges in complex SoCs *Strong understanding of clock synchronization strategies and metastability management *Deep knowledge of power management techniques and implementation *Experience with integration-specific verification methodologies *Proficiency in debugging complex system-level issues *Advanced understanding of timing analysis and constraints at the integration level Advanced Capabilities: *Ability to identify and address system-level bottlenecks affecting performance *Experience optimizing interconnect architectures for bandwidth and latency requirements *Knowledge of security isolation requirements for modern SoCs *Skill in balancing conflicting requirements from multiple IP teams *Experience mentoring junior engineers on integration methodologies *Ability to influence architectural decisions based on integration considerations At the MTS level, you would be expected to independently lead major integration efforts, serve as a technical authority on integration challenges, and contribute to architectural decisions that affect the entire SoC design. AMD (Dont Share AMD Profiles)

Preferred candidate profile