1233 Protocols Jobs - Page 35

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Good knowledge of C programming, Data Structures Exposure to embedded software and/or driver development Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Atleast 2-5 yrs of experience/exposure in below areas. Basic understanding of system level concepts such as Caches/DMA/IRQ handling is desired Knowledge of basic network protocols (TCP/UDP/ARP) OR understanding of 802.11 specification is desired Exposure to Linux Kernel internals and experience with low level kernel programming such as writing/modifying networking/wireless LAN device drivers or Protocol handlers is a plus

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Good knowledge of C programming, Data Structures Exposure to embedded software and/or driver development Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Atleast 2-5 yrs of experience/exposure in below areas. Basic understanding of system level concepts such as Caches/DMA/IRQ handling is desired Knowledge of basic network protocols (TCP/UDP/ARP) OR understanding of 802.11 specification is desired Exposure to Linux Kernel internals and experience with low level kernel programming such as writing/modifying networking/wireless LAN device drivers or Protocol handlers is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: You will be joining the WLAN device driver/middleware team, working on design, development and debugging software features for Qualcomm WLAN drivers and middleware. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. 3-5 years of experience Competent in C Programming and data structures. Very good understanding and experience of Operating System concepts, Linux Kernel , Linux Device Drivers . Thorough in Linux OS concepts (Threads, Synchronization, Memory Management etc.). Must have exposure to the WLAN technology, 802.11 and other networking protocols is preferred. Good Analytical and problem solving skills. Proficient verbal and written communication skills. Responsibilities: Provide software engineering solutions for development projects in the Wi-Fi Connectivity Group. Work on/with multiple layers of the WLAN software stack, including user space and kernel space in different operating environments. Involve debugging in different software environments and on hardware

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: 3 to 15 years of work experience in ASIC/SoC Design Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Excellent oral and written communications skills Proactive, creative, curious, motivated to learn and contribute with good collaboration skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational 2+ years of experience with a Bachelors/ Masters degree in Electrical engineering

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ Years of Experience in Logic design /micro-architecture / RTL coding Must have hands on experience with SoC design, synthesis and timing analysis for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Work closely with the SoC DFT, Physical Design and STA teams Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as DesignCompiler, Genus, FusionCompiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Work as part of WIFI Host driver team on tasks that are related to WIFI Standard protocols- WIFI7/WIFI8. You will be working on wireless drivers, hostapd/wpa_supplicant, protocol, and other features across the range of our wireless access point solutions. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. 1. 4+ years of experience in software feature development using C/C++ programming languages2. Good Understanding of Linux Kernel internals and experience with low level kernel programming such as writing/modifying device drivers preferred3. Good knowledge of network protocols such as TCP/UDP/IPv4/IPv6/ARP/DHCP4. Good understanding of Linux network stack and any experience with wireless LAN (WiFi) device drivers is a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Minimum 4 to 8 years of work experience in ASIC RTL Design, Synthesis, STA & FVExperience in Logic design/micro-architecture/RTL coding is a must.Must have hands on experience with design and integration of complex multi clock domain blocksExperience in Verilog/System-Verilog is a must.Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architectureHands on experience in Multi Clock designs, Asynchronous interface is a must.Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.Work closely with the Design verification and validation teams for pre/post Silicon debugHands on experience in Low power design is preferableExperience in Synthesis / Understanding of timing concepts for ASIC is must Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must . Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must . Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required . Hands on experience in Multi Clock designs, Asynchronous interface is a must . Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience

Job Area: Interns Group, Interns Group > Interim Engineering Intern - HW Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: We know our employees ideas change the world. For more than three decades, weve been a global leader in mobile technology, continually pushing the boundaries of whats possible. Working with customers across industries "” from automotive to health care, from smart cities to robotics"” we continue to accelerate innovation and unlock new possibilities in a time where everything is connected. By joining the Qualcomm family, you too can bring the future forward faster. SOC & Hard Macro Physical Design SOC Validation & Debug RF & Analog Layout RF/Analog/Mixed Signal/Power IC Design Low Power Design Board and FPGA Design Digital ASIC Design Design/SOC Verification CAD Solution Engineer Design for Test (DFT) CPU Design Must have educational background in one or more of the following areas: Verifying SoC with embedded RISC/DSP processors, communications/ networking ASICs. Verilog or VHDL, C/C++, Tcl/Perl/shell-scripting. RTL design experience and/or strong OO programming knowledge Knowledge of wireless/wired communications and protocols or graphics/video multi-media is a plus. Knowledge in PLL, LNA, OpAmp, CMOS, ADC/DAC, Cadence, SpectreRF, or Layout is required in RF/Analog/Mixed Signal IC Design. Excellent analytical and problem solving skills. Ability to collaborate and work in teams. Good verbal and written communication skill Educational Background:Masters, BachelorsElectrical Engineering , VLSI , Embedded and VLSI , ECE

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: erification engineer candidate will be responsible to manage I2C/I3C/SPI/UART/UFS/ /high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage (code, toggle, functional). Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solutions to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 5+ years experience in verification domain. Prior work experience on IP level or Soc level. Prior work on Serial Protocols I2C/I3C/SPI/UART , SDCC , UFS ,USB Good understanding of processor-based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AHB, AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: Bachelors degree in Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Over 8+ years of related work experience Possesses in-depth knowledge and hands-on experience with peripheral protocols such as CXL3.0 and PCIe Gen5/6 Validation, along with exposure to server chips. Skilled in bare metal/Linux driver development and proficient in C programming. Experienced in complex SoC software development and hardware validation testing, covering functional, performance, compliance, and power aspects. Proficient with debug and lab tools, including Lauterbach, oscilloscopes, and protocol analyzers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM, System Verilog coding Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Communication and collaboration skills to work with a large world-wide design organization Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Proficiency in any of the Scripting languages (Python or Perl) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces. Additional 3 to 5 years of experience Hands on experience with embedded distributions such as Yocto. Thorough Embedded C programming knowledge & experience (especially pointers, structures, linked lists etc.,) & Assembly programming knowledge Hands On Experience for Device Driver development with any of standard protocols such as SPI, UART, USB etc., Thorough knowledge and experience on operating systems and kernel Thorough RTOS knowledge and experience (Mutex, spinlocks, Queues, Signaling, Events, Deferred function calls & Callbacks, Multi-thread & multi-process environments, Concurrency Scenarios etc.,), Linux Knowledge, Kernel & User Space knowledge Thorough experience of Operating systems, Microprocessor / computer architecture. Strong analytical and debugging skills Hardware and architectural knowledge / experience (Processor Architecture, Cache, interrupts, Memory barriers, Strong ordering etc.,) Emulator, simulator environment & JTAG debugging knowledge / experience Leading a team of junior engineers for managing design, development, delivery and execution of various projects through entire software development life cycle Ownership, accountability, commitment and delivery of project commitments Technology leadership and representation Nice to Have - Hands On Experience or knowledge for Inter Processor Communication Protocol, Debug Logging framework, Heap Management & Timer implementations Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: In this position you will join the team responsible for the security architecture of Qualcomm Snapdragon processors. The team works at a system level spanning across hardware, software and infrastructure while striving for industry-leading solutions. This team interacts with product management, customers (e.g., OEMs), partners, HW/SW engineering, and Services engineering teams to find the optimal Security solution. Snapdragon processors are utilized in a variety of devices, including mobile phones, laptops, automotive systems, and data centers, each with distinct security needs. These processors are engineered to address most of these requirements, encompassing a wide range of security technologies found in consumer electronics, such as Root of Trust, Integrated Secure Element, Virtualization, and Confidential Compute. Minimum Qualifications 10+ years industry experience in SoC Security encompassing both architecture and design 5+ years industry experience in Compute and/or Data Centre SoC Architecture Demonstrated expertise in Security Technologies (Root of Trust, TEE, Access Control, I/O Security) Proficient in Confidential Compute Architecture (RME, TDX, SEV-SNP, TDISP) Strong understanding of Security Software Architecture for Compute and Data Centers, with a focus on Secure Boot. Skilled in HW/SW threat analysis Strong capabilities in creating and presenting architecture-level documentation. Preferred Qualifications Proficient in isolation-related extensions, including TrustZone, Virtualization, and RME. Extensive knowledge of Server Platform security architecture covering lifecycle/debug management, provisioning, attestation/measurement. Expertise in Applied Cryptography and Protocols. Knowledgeable about Security Certification Processes and (such as OCP) Excellent communication and teamwork skills. Leadership and management experience at the project level Key Responsibilities Establish system security requirements (both hardware and software) for Server SoC focusing on functionality, performance, and security levels. Specify and review the architecture and implementation of System/SoC level security mechanisms. Conduct platform security threat analysis. Perform competitive analysis of security systems and features Explore future and roadmap server security-related technologies. Serve as the technical interface to product management and standards teams. Minimum Qualifications: Bachelors degree in engineering, Computer Science, or related field and 8+ years of Security Engineering or related work experience. ORMasters degree in engineering, Computer Science, or related field and 7+ years of Security Engineering or related work experience.ORPhD in Engineering, Computer Science, or related field and 6+ years of Security Engineering or related work experience. Note References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Join Qualcomms cutting-edge hardware engineering team to drive the design verification of next-generation SoCs, with a focus on wireless technologies including WLAN (IEEE 802.11). You will work on IP and subsystem-level verification, collaborating with cross-functional teams to deliver high-performance, low-power silicon solutions. A strong understanding of on-chip buses and bridges is essential to ensure seamless integration and performance across subsystems. Key Responsibilities Develop and execute verification plans for complex SoC designs and IP blocks. Architect and implement testbenches using SystemVerilog and UVM/OVM methodologies. Perform RTL verification, simulation, and debugging. Collaborate with design, architecture, and software teams to ensure functional correctness. Contribute to IP design reviews and sign-off processes. Support post-silicon validation and bring-up activities. Analyze and verify interconnects, buses (e.g., AMBA AXI/AHB/APB), and bridges for performance and protocol compliance. Conduct CPU subsystem verification including coherency, cache behavior, and interrupt handling. Perform power-aware verification using UPF/CPF and validate low-power design intent. Execute performance verification to ensure bandwidth, latency, and throughput targets are met. Preferred Skills & Experience 2"“15 years of experience in digital design and verification. Deep understanding of bus protocols and bridge logic, including hands-on experience with AXI, AHB, and APB. Experience with CPU subsystem verification and performance modeling. Familiarity with wireless protocols (IEEE 802.11 a/b/g/n/ac/ax/be) is a plus. Proficiency in SystemVerilog, UVM/OVM, Verilog, and scripting languages (Perl, Tcl, Python). Experience with power-aware verification methodologies and tools (e.g., UPF, CPF). Familiarity with performance verification techniques and metrics. Exposure to tools like Clearcase/Perforce and simulation/debug environments. Strong analytical, debugging, and communication skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications Bachelors or Masters degree in Electrical/Electronics Engineering, Computer Science, or related field. Relevant experience in hardware design and verification.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: General Summary Join Qualcomms Wireless IP team to design and develop cutting-edge RTL for next-generation cellular and Wi-Fi modem IPs used in mobile, wearable, and IoT platforms. You will work on high-performance, low-power digital designs across the full VLSI development cycle"”from architecture and micro-architecture to RTL implementation and SoC integration. This role offers the opportunity to collaborate with global teams and contribute to market-leading wireless solutions. Key Responsibilities Design and implement RTL for wireless modem IPs and SoC subsystems using Verilog/SystemVerilog. Develop micro-architecture specifications and deliver high-quality, synthesizable RTL. Integrate complex subsystems into SoC environments and support design convergence. Collaborate with system architects, verification, SoC, software, DFT, and physical design teams. Apply low-power design techniques including clock gating, power gating, and multi-voltage domains. Analyze and optimize for performance, area, and power. Ensure protocol compliance and performance of interconnects, buses (AXI, AHB, APB), and bridges. Conduct CDC and lint checks using tools like Spyglass and resolve waivers. Participate in post-silicon debug and bring-up activities. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Skills & Experience 2"“15 years of experience in digital front-end ASIC/RTL design. Strong expertise in Verilog/SystemVerilog RTL coding and micro-architecture development. Familiarity with wireless protocols such as IEEE 802.11 (a/b/g/n/ac/ax/be), LTE, or 5G NR is highly desirable. Solid understanding of bus protocols (AXI, AHB, APB) and bridge logic. Experience with wireless modem IPs or similar high-performance digital blocks is a plus. Familiarity with low-power design methodologies and CDC handling. Hands-on experience with tools like Spyglass, 0-in, Design Compiler, PrimeTime, and simulation environments. Exposure to post-silicon debug and SoC integration challenges. Strong documentation and communication skills. Self-motivated with a collaborative mindset and ability to work with minimal supervision. Minimum Qualifications Bachelors or Masters degree in Electronics, VLSI, Communications, or related field. Proven experience in RTL design and SoC development.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly experienced Network-on-Chip (NoC) Architecture and Systems Engineer to join our innovative and dynamic NoC systems team. The ideal candidate will have a deep understanding of NoC architectures, system design, and various communication protocols such as PCIe, CXL, and AMBA CHI. This role involves designing, implementing, and optimizing NoC solutions for complex SoC (System on Chip) designs, collaborating with cross-functional teams, and driving research and development initiatives to stay at the forefront of technology. Key Responsibilities: Architecture Design: Develop and optimize NoC architectures for high-performance SoC designs, including routers, interconnects, and communication protocols. Protocol Expertise: Design and implement NoC solutions that support various communication protocols such as PCIe, CXL, and AMBA CHI. System understanding: Understanding of NoC solutions for overall SoC design, ensuring seamless communication between various IP blocks and subsystems. Performance Analysis: Conduct detailed performance analysis and benchmarking of NoC designs to identify bottlenecks and areas for improvement. Collaboration: Work closely with hardware, software, and verification engineers to ensure that NoC designs meet system requirements and performance goals. Troubleshooting: Identify and resolve complex issues in NoC design and simulation. Research and Development: Stay updated with the latest advancements in NoC technology and contribute to the development of new methodologies and tools. Actively participate in research projects to explore new NoC architectures and protocols. Primary Skills Proficient in NoC design and optimization techniques. Strong understanding of digital design principles and SoC architecture. Experience with hardware description languages (HDLs) such as Verilog. Familiarity with SystemC and C++ for modeling and simulation is a plus. Knowledge of NoC simulation tools and environments is a plus (e.g., Gem5, Noxim). Experience with performance analysis and benchmarking tools. Expertise in various communication protocols such as PCIe, CXL, and AMBA CHI is a plus. Soft Skills Excellent problem-solving and analytical skills. Strong communication and collaboration abilities. Ability to work independently and in a team environment. Attention to detail and a commitment to quality. Enthusiasm for research and innovation. Preferred Skills: Experience with Network-on-Chip, high-performance computing and parallel processing. Knowledge of ASIC design flows. Familiarity with scripting languages (e.g., Python, Perl). Experience with version control systems (e.g., Git). Background in NoC design, NoC Architecture, low-power design and optimization. Publication history in relevant technical journals or conferences. Qualifications: Education: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Experience: 6 to 11 years of experience in NoC architecture and systems design. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a DV Engineer with a focus on SOC design verification, you will work to understand the internal requirements and complexities of our highly complex auto, compute, mobile, XR-VR, IoT SOCs and architect the required verification strategy. You will help set up methodologies, develop test plans, and verify that the design meets the highest quality standards. We believe in early involvement of DV, so you will also participate in architecture/product definition through early involvement in the product life-cycle. Preferred qualifications B.E/B.Tech/M.E/M.Tech in Electronics with 5+ year experience in verification domain. Strong fundamentals in digital ASIC verification Experience in IP/SS/SoC level verification of medium to high complexity design Familiarity with system level HW and SW Debug techniques and Verification requirements A good understanding of the complete verification life cycle (test plan, testbench through coverage closure) Strong System Verilog/UVM based verification skills & Experience with Assertion & coverage-based verification methodology Experience w/ PSS or higher-level test construction languages is an added advantage Working knowledge of Interconnect architecture and Bus protocols like AMBA - ACE/CHI/AXI Good understanding of low power design techniques Proficient with low power SoC design constructs such as clock gates, level shifters, isolation cells and state retention cells. Experience with UPF/CPF based power aware verification. Working knowledge of GLS , PAGLS and scripting languages such as Perl, Python is a plus Prior work on NoC/Interconnects end to end verification with solid understanding on to Bus protocols, Coherency, Performance, Latency, clock gating etc. Knowledge of one or more of Multimedia design blocks such as Display/Camera/Video/GFx Knowledge of one or more of peripheral blocks verification such as PCIe/USB/UFS/I3C Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.Roles and Responsibilities Define verification architecture, develop test plans and build verification environment Work with design team to understand design intent and bring up verification plans and schedules Verify Subsystems and Full SoC using advanced verification methodologies Build agents and checkers from scratch. Perform and write test plan from design architecture specs and/or protocol standard Develop test plan to verify all low power aspects across all modes of verification- RTL, PA-RTL, PA-GLS and Formal Own end to end DV tasks from coding Test bench and test cases, write assertions, debugging UPF and RTL and achieving all coverage goals Assist in silicon bring-up, debug and bring-up activities Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Overview: Person will be responsible for developing next generation SoCs for mobile products and its adjacencies. The role will require the candidate to understand and work on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. The person is also responsible for overseeing physical design and verification aspects. : - Full chip design for multi million gates SoC- Digital design and development (RTL)- Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification- Manage IP dependencies, planning and tracking of all front end design related tasks- Driving the project milestones across the design, verification and physical implementations Minimum Qualifications: - Minimum 15 years of solid experience SoC design- Developing architecture and micro-architecture from specs- Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC- Understanding of Memory controller designs and Microprocessors is an added advantage- Understanding of Chip IO design and packaging is an added advantage- Familiarity with various bus protocols like AHB, AXI is highly desired- Ability to review top level test plans- Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC- Working knowledge of timing closure is a must - Should have good post silicon bring up and debug experience - Should have good SoC integration exposure and its challenges - Should have good exposure to design verification aspects - Having SoC specification to GDS to commercialization experience is highly desired - Needs to makes effective and timely decisions, even with incomplete information.- Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas.- Provides direction, mentoring, and leadership to a small to medium sized groups.- Should possess strong communication and leadership skills to ensure effective communication with Program

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum 4 to 6 years of work experience in ASIC RTL Design Experience in Logic design/micro-architecture/RTL coding is a must. Must have hands on experience with design and integration of complex multi clock domain blocks Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of Automotive System Designs, Functional Safety, Memory controller designs and microprocessors is an added advantage Work closely with the Design verification and validation teams for pre/post Silicon debug Hands on experience in Low power design is preferable Experience in Synthesis / Understanding of timing concepts for ASIC is must

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Serdes PHY Analog Design Job Function BDC SerDes Mixed-Signal design team is actively looking for experienced (4-12+ years) analog circuit designers to work on high speed SerDes PHYs . You will be directly involved in delivering next-generation custom PHY designs for SoCs and will be part of a growing team involved in architecture analysis in leading-nodes - finfets & beyond. Design goals include low-power analog designs to address Qualcomm's low-power wireless products. Responsibilities Hands-on experience - Analog circuit design Experience in designing multiple analog building blocks - LDO, high speed TX and RX (Equalizer, Sampler, PI, Deserializer etc) , Bias, Reference etc. Analog and or Digital PLLs for frequency synthesis and/or SerDes applications" Charge pump, loop filter, VCO/DCO, PFD/TDC, high speed dividers. PLL Loop Dynamics, Jitter sources and modeling (RJ & DJ) Ability to take a design, perform schematic to post layout verification, integration sign-off to post silicon bring up. Work closely with RTL, DD, PD, DV and SoC verification teams to integrate the PHY. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skills & Experience For lead position, candidates must have performed PHY Lead roles which include PHY integration to SOC & interaction with post silicon teams like HSIO, ATE, SVE, CE etc. Understanding of advance Finfet process effects on designs and layout is required. Experience in using SPICE simulators, adexl & virtuoso. Experience with post-Si bring-up and debug is must. Good understanding on peripheral PHYs (USBs, UFS, PCIe) protocols is added advantage. Master/Bachelor in Electronics Shell/Perl-python scripting to automate circuit design and verification work. Able to work with teams across the globe and possess good communication and presentation skills. Preferred Mixed signal design experience Keywords Analog circuit Design, Rx, Tx, PLL, SerDes, PHY, Serializer, Deserializer, VCO, High-speed Trans receiver

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Ownership of System Memory Management [SMMU] IP test bench and collaterals for the next generation System-on-chip (SoC) for smartphones, tablets and other product categories. System Memory Management Unit does virtual to physical address translation, dynamic allocation and access control of DDR memory, designed as per ARM SMMU architecture spec. Job responsibilities include Ownership of DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage) Develop test plan and test cases to cover design feature set, follow up with stake holders on code coverage, functional coverage closure at different levels of test bench Work closely with System Architects, Design, emulation teams on failure debugs, code/functional coverage closure Debug of regression signatures and identifying bug fixes Developing/Deploying scripts/tools for validation (Certitude, VC Formal, Fishtail) Debug and root cause post silicon issues in collaboration with Design, SW and test teams Work with SoC level performance modeling team on latency, bandwidth analysis Required skillset include Strong debugging, Analytical and problem-solving skills Expertise on UVM, System Verilog coding Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture Experience in developing Monitors, Scoreboards, Sequencers that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved Post-si bring-up and HW-SW debug experience would be a plus. Knowledge & exposure to silicon debug tool chains would be an added advantage Communication and collaboration skills to work with a large world-wide design organization Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Proficiency in any of the Scripting languages (Python or Perl)

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: As an Engineer / Sr. Engineer / Lead Engineer in the WLAN FIRMWARE HALPHY Group, you will be designing, developing, unit testing, bug fixing and maintaining WLAN firmware and HALPHY components that implements functional aspects of WLAN features on low memory foot print processors that will work in tandem with device drivers running on the host processors. The host driver and the firmware implement the WLAN drivers on the Qualcomms WLAN SoC platforms. You will be working on cutting edge WiFi technologies, solving challenging WiFi design & performance issues and working with some of the leading WiFi ODMs & OEMs across the globe on their sometimes high pressure & tough timelines. At least 2-8 years of relevant hands-on technical experience in WLAN/Linux driver development with a record of strong individual technical achievement Strong programming skills in C. This position is for wireless LAN (WLAN) RF level development. The role requires knowledge of WLAN RF basics, RF system level programming, WLAN RF performance enhancement techniques, L2/L1 features, and writing APIs for upper layers. Implement RF calibration algorithms, Crystal calibration algorithms, RF level debugging, Flash/EEPROM programming, Generating RF initialization sequences for WLAN chipsets, Writing APIs for RF equipment. Responsibilities Design, develop, unit test and documentation of Firmware for AP SoC. Bring up the driver and unit test the driver features in the new AP. Optimize the driver for maximum performance. Bug analysis/fixing of the issues during product verification stage and customer reported issues. Travel to customer site for bug fixing. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Skills/Experience At least 2-8 years of relevant hands-on technical experience in WLAN/Linux driver development with a record of strong individual technical achievement - Strong programming skills in C - Must have hands on working experience working on real-time embedded systems - Must have hands on experience in solving complex system issues with good problem solving skills - Experience in working on Firmware in small memory footprint processors is a BIG plus - Hands on experience in Networking driver development, Ethernet and Wireless LAN driver development preferred - Hands on knowledge and experience on IP Networking technologies is a plus - RF level knowledge is a plus - Excellent verbal and written communication skills - Experience in Wireless LAN protocols is a BIG plus - Should be able to work in an aggressive, high pressure environment Educational BE/BTech/MTech in Computer Science or in Electronics preferred with proven success in a challenging academic program.