Principal Engineer, Physical Design Clocking

You will be part of the SoC Clocking team, focusing on next-generation Networking and Edge SoC designs. Your responsibilities will include product pathfinding, end-to-end clocking architecture, clock distribution, and overseeing SoC clock implementation and Sign off. You should have experience in SoC Clock Architecture, clock distribution, and system-level clocking. Additionally, hands-on experience with spice, clock jitter simulations, and different jitter components is required. You will work on clocking methodologies and guidelines for IPs or SoCs and create scalable flows for clocking infrastructure to enhance performance and power in the design. Collaboration with Platform, package, IP, and SoC design teams is essential to drive best-in-class clocking solutions. A good understanding of Physical design and SoC timing analysis would be beneficial. Proficiency in Perl, TCL Scripting Skills is necessary. Qualifications - Bachelors (B.Tech) or Masters (M.Tech) in Electrical Engineering or related areas. - At least 18+ years of experience in SoC clock architecture, clock distribution, and clock implementation. - Hands-on experience with Synopsys, cadence APR/Clock implementation tools. - Good understanding of System-level clocking. - Proficient in scripting languages (Tcl, Perl, Python). - Ability to communicate effectively with multiple global cross-functional teams. This is an Experienced Hire job role with a requirement for on-site presence at Shift 1 (India). The primary location for this role is in India, Bangalore. Xeon and Networking Engineering (XNE) business group focuses on the development and integration of XEON and Networking SOC's and critical IP's to sustain Intel's Xeon and 5G networking roadmap. Please note that this role is a Position of Trust, requiring consent to and successful completion of an extended Background Investigation, which includes various checks. The work model for this role is subject to change.,