Physical Design/STA/EMIR Engineers - Pune

Urgent Hiring VLSI Physical Design / STA / EMIR Engineers (Immediate Joiners Only) | Pune Location Location: Pune Notice Period: Only Immediate Joiners Hiring Duration: Till 3rd Week of June Mode: Full-time Opportunity 1. Physical Design Engineer Experience: 4 to 6 Years Key Responsibilities: Full RTL-to-GDSII flow execution including floorplanning, power planning, placement, CTS, routing, DRC/LVS closure. Work on advanced technology nodes (7nm/5nm and below). Experience in hierarchical and flat implementation. Ownership of block-level PnR, timing closure, IR/EM, and physical verification. Interfacing with cross-functional teams RTL, DFT, PD, and verification teams. Required Skills: Strong expertise in tools like ICC2, Innovus, PrimeTime, RedHawk. Scripting in TCL/Perl/Shell to automate design tasks. Understanding of timing, noise, congestion, and power trade-offs. Good analytical and debugging skills. 2. STA Engineer Experience: 6 to 12 Years Key Responsibilities: Responsible for full-chip/block-level Static Timing Analysis and sign-off. Support physical design and timing convergence teams. Create and validate timing constraints (SDC), analyze paths, and suggest optimizations. Perform ECO implementation and validation. Sign-off checks including noise, DRC, SI, IR, and leakage power. Required Skills: Expert in using Synopsys PrimeTime (or equivalent STA tool). Deep understanding of timing concepts – setup, hold, skew, clock uncertainty, etc. Proficiency in scripting (TCL/Perl). Experience with multi-corner, multi-mode (MCMM) STA. Strong debugging and closure experience across multiple tapeouts. 3. EMIR Engineer (IR/EM Analysis) Experience: 5 to 9 Years Key Responsibilities: Perform IR drop and Electromigration (EM) analysis using tools like RedHawk, Voltus. Define EM/IR methodologies and flows. Collaborate with design teams to improve power grid design and robustness. Ensure sign-off quality results for high-performance SoCs. Create automated checks and regression flows. Required Skills: Strong knowledge of power integrity issues and reliability concerns at advanced nodes. Familiarity with power grid design, decap planning, and current estimation. Hands-on experience with EMIR tools (Ansys RedHawk, Cadence Voltus). Good knowledge of PnR flow and integration with IR/EM requirements. Qualifications for All Roles: B.E/B.Tech or M.E/M.Tech in Electronics/VLSI/EEE. Proven tapeout experience in complex SoCs. Excellent communication and problem-solving skills. Why Join Us? Work with cutting-edge technology on advanced nodes. Collaborative team environment with domain experts. High-impact, visible roles with leading semiconductor customers. Apply Now – Immediate joiners preferred. Note: This requirement is open only till the 3rd week of June .