4 Memory Hierarchies Jobs

We are seeking a seasoned Software Engineer with a strong background in computer architecture or networking. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions by developing high-quality system software, optimizing algorithms, building performance models, and collaborating closely with hardware teams. Roles and Responsibilities: Develop system software in Python and C++ . Develop core software optimization algorithms and platforms. Build performance models of different IPs (Intellectual Properties). Work closely with hardware teams to implement configuration knobs for IPs. Execute verification test plans to produce high quality software. Participate in the design, development, and architecture of scalable and reliable software solutions. Contribute to system-level architecture discussions and propose improvements or optimizations. Collaborate with cross-functional teams, including hardware design and verification teams, to ensure seamless integration and product quality. Debug and troubleshoot software issues, ensuring robust and efficient performance. Document code, designs, and processes for maintainability and knowledge sharing. Qualifications and Preferred Skills: Strong object-oriented programming skills with Python and C++ . Expert level knowledge of Data Structures and Algorithms . Expert level knowledge of building concurrent system models . Strong understanding of computer architecture, memory hierarchies, and networking concepts . Understanding of software systems design and modeling. Experience with modern code development practices: Git, CI (Continuous Integration), UI (User Interface) . Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills. Ability to analyze complex technical problems and propose effective solutions. QUALIFICATION: BS, MS in Computer Science, Computer Engineering or Electrical Engineering.

We are seeking a seasoned Software Verification Engineer with a strong background in computer architecture or networking. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions by developing high-quality software, optimizing algorithms, building performance models, and executing comprehensive verification test plans. Roles and Responsibilities: Develop system software in Python and C++ . Develop core software optimization algorithms and platforms. Build performance models of different IPs (Intellectual Properties). Work closely with hardware teams to implement configuration knobs for IPs. Execute verification test plans to produce high-quality software, ensuring functionality and performance meet specifications. Participate in the design, development, and architecture of scalable and reliable software solutions. Contribute to system-level architecture discussions and propose improvements or optimizations. Collaborate with cross-functional teams, including hardware design and development teams, to ensure comprehensive test coverage and timely resolution of issues. Document test results and report defects clearly and concisely. Qualifications and Preferred Skills: Strong object-oriented programming skills with Python and C++ . Expert level knowledge of Data Structures and Algorithms . Expert level knowledge of building concurrent system models . Strong understanding of computer architecture, memory hierarchies, and networking concepts . Understanding of software systems design and modeling. Experience with modern code development practices: Git, CI (Continuous Integration), UI (User Interface) . Excellent problem-solving skills and attention to detail. Strong communication and collaboration skills. Ability to analyze complex technical problems and propose effective solutions. Familiarity with verification methodologies and tools used in the semiconductor or CAD industry. QUALIFICATION: BS, MS in Computer Science, Computer Engineering or Electrical Engineering.

As an experienced professional in ASIC development with a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, you will be leading a team of engineers in Bengaluru to deliver AI/ML compute intensive IPs and subsystems. With 8 years of experience in Verilog/SystemVerilog, VHDL, or Chisel, and 4 years of people management expertise, you will collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. Your responsibilities will include taking ownership of complex IPs or subsystems, implementing RTL, and driving design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Additionally, you will be tasked with identifying and driving power, performance, and area improvements for the domains owned. Your role will involve working on cutting-edge SoCs used to accelerate machine learning computation in data centers. You will be solving technical issues with innovative micro-architecture and practical logic solutions, and evaluating design options with complexity, performance, power, and area in mind. Furthermore, you will contribute to the innovation behind products loved by millions worldwide, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The future of AI/ML hardware acceleration awaits you in this role, where you will have the opportunity to shape cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. Your contributions will play a crucial role in delivering high-quality designs for next-generation data center accelerators, collaborating with various teams such as architecture, verification, power and performance, and physical design. The Technical Infrastructure team at Google is responsible for the architecture that keeps everything running smoothly online. From data centers to the next generation of Google platforms, this team ensures Google's product portfolio remains at the forefront of innovation. By joining this team, you will play a key role in maintaining networks, ensuring users have the best and fastest experience possible.,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. You should possess at least 5 years of experience in ASIC development with Verilog/SystemVerilog and VHDL. It is essential to have experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Additionally, experience in micro-architecture and design of subsystems is required. Preferred qualifications: Ideally, you should have experience in SoC designs and integration flows. Proficiency in scripting languages such as Python or Perl would be beneficial. Knowledge of high performance and low power design techniques is preferred, along with an understanding of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. About the job: As a member of our team, you will contribute to shaping the future of AI/ML hardware acceleration, focusing on cutting-edge TPU (Tensor Processing Unit) technology that drives Google's most demanding AI/ML applications. Your responsibilities will involve verifying complex digital designs, specifically related to TPU architecture and its integration within AI/ML-driven systems. You will work on ASICs used to enhance data center traffic, collaborating with various teams to deliver high-quality designs for next-generation data center accelerators. Innovation, problem-solving, and evaluation of design options will be key aspects of your role, with a focus on micro-architecture and logic solutions. The ML, Systems, & Cloud AI (MSCA) organization at Google is responsible for designing, implementing, and managing the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. Prioritizing security, efficiency, and reliability, the team works towards shaping the future of hyperscale computing, impacting users worldwide. Responsibilities: - Own microarchitecture and implementation of subsystems in the data center domain. - Collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. - Perform Quality check flows like Lint, CDC, RDC, VCLP. - Drive design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. - Identify and implement power, performance, and area improvements for the domains owned.,