2 Makefile Jobs

As an experienced professional with 7-9 years of experience, you will be responsible for executing customer projects independently with minimal supervision in the field of VLSI Frontend Backend or Analog design. Your role will involve guiding team members technically and taking ownership of specific tasks/modules related to RTL Design, Module Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. You will lead the team to achieve results, complete assigned tasks successfully and on-time, and anticipate, diagnose, and resolve problems as necessary. Your responsibilities will also include ensuring on-time quality delivery approved by the project manager and client, automating design tasks flows, writing scripts to generate reports, and coming up with innovative ideas to reduce design cycle time and cost. Additionally, you will be expected to write papers, file patents, and devise new design approaches. To measure the outcomes of your work, quality will be verified using relevant metrics by UST Manager/Client Manager, timely delivery will be assessed based on relevant metrics, and the reduction in cycle time and cost using innovative approaches will be monitored. The number of papers published, patents filed, and trainings presented to the team will also be considered. Your outputs are expected to demonstrate high quality deliverables with zero bugs in the design/circuit design, clean delivery of the design/module, meeting functional specs/design guidelines without deviation, and thorough documentation of tasks and work performed. Timely delivery, teamwork, innovation, and creativity will be key aspects of your role, along with participation in technical discussions and training forums. Your skills should include proficiency in languages and programming skills such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. You should have experience with EDA tools like Cadence, Synopsys, and Mentor tool sets, as well as technical knowledge in IP spec architecture design, bus protocols, physical design, circuit design, analog layout, synthesis, DFT, floorplan, clocks, P&R, STA, extraction, physical verification, and more. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the ability to interact with team members and clients effectively are essential. You should also be well-versed in using available EDA tools, delivering tasks on time per quality guidelines, understanding standard specs and functional documents, and continuously learning new skills as needed. If you have led and executed projects in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, Analog Layout, and possess a good understanding of design flow and methodologies, this role could be a great fit for you. Additionally, experience in analog circuit design and verifications, knowledge of TSMC FinFet technologies, and familiarity with Cadence Virtuoso circuit design suite would be beneficial. In this role, you will be responsible for circuit design and verification of analog modules like Voltage regulator, LDOs, developing circuit architecture, optimizing designs, guiding layout engineers, problem-solving, and effective communication skills. Desired skills include solid CMOS Analog design fundamentals, hands-on experience with Cadence Virtuoso, technical knowledge of power-performance trade-offs, understanding device parameter variation, and being a good team player in a multi-site work environment. Join us at UST, a global digital transformation solutions provider, where you will work alongside the world's best companies to make a real impact through transformation. With deep domain expertise, innovation, and agility, UST partners with clients to embed innovation and create boundless impact, touching billions of lives in the process.,

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Job Duties: We are seeking a motivated and quick-to-learn Software Engineer to join the Electronic Design Automation (EDA) field, specifically to advance the Questa formal verification product family. In this multifaceted role, you will be involved in the entire project lifecycle, from writing functional specifications to designing algorithms, coding, and creating test plans. Collaboration with a team of talented engineers and supporting top-tier industry customers will be essential. The ideal candidate will have extensive software development experience, particularly in developing and customizing components around graph-based formal models, with hands-on programming and expertise in crafting efficient netlist representation models for formal applications. Our primary responsibilities will include crafting and developing new features, customizing existing solutions, and improving software components for formal verification, ensuring quality, scalability, modifiability, and testability. You will collaborate with other engineering teams, take ownership of specific components, and drive them to excellence. Additionally, you will help drive the best software practices within the team and mentor other specialists as needed, all while contributing to the businesss overall needs. Job Qualifications: We require candidates to have a BE/B-Tech/M.Tech in CSE/ECE from a reputed engineering college. We are looking for candidates with 5-10 years of software experience, preferably in the Design and Verification domain. Expert in C++ , design patterns, and algorithms. Strong understanding of data structures and algorithm complexities . Proficient in advanced data structures and their applications. Expert in one of the following hardware description languages: Verilog , System Verilog , or VHDL . Knowledge of scripting languages like Perl , Python , Bash , or Tcl . Proficient with development tools such as Makefile , gdb , valgrind , perforce/git , gcov , editors , and IDEs . Strong problem-solving and analytical skills . Experienced in the development and delivery of multi-man-month projects from start to finish. Familiarity with Linux platforms . Exposure to formal-based verification methodologies (model checking, equivalence checking, automated reasoning) is a plus. Soft Skills: Self-motivated and committed to work. Strong team player with the ability to work independently. Hardworking, sincere, and open to constructive feedback. Able to work in challenging environments and collaborate effectively with multi-cultural technical teams. Good to Have: Exposure to Synthesis, Simulation, and other verification methodologies like Assertion, Coverage, etc. Strong presentation, listening, and communication skills for effective team interactions.