59 Isa Jobs

As a Senior Manager, you will be responsible for overseeing operations and leading a team in Switzerland. Reporting directly to the Director and above, you will play a key role in driving the success of the organization in the designated region. Your primary focus will be on managing the day-to-day activities, setting strategic goals, and ensuring that the team meets performance targets. You will be required to provide leadership, guidance, and support to team members to help them achieve their full potential. The ideal candidate for this role should have strong leadership skills, excellent communication abilities, and a proven track record of success in a managerial position. Additionally, the ability to work effectively in a fast-paced environment and adapt to changing priorities is essential. This is a full-time position with work timings from 9:00 AM to 5:30 PM IST. If you are looking for a challenging opportunity to showcase your leadership skills and make a significant impact, we invite you to apply for this role.,

We are looking for a motivated and experienced Product Customization Engineer to join our team. In this role, you will contribute to a dynamic team focused on delivering custom solutions to customers" unique applications. Your primary responsibility will be to provide technical support for Fisher Rotary and Sliding Stem valves, collaborating closely with various teams to ensure seamless quote and order execution. Your responsibilities will include handling daily order activities related to product design modifications, supporting the quotation process, performing detailed design calculations and engineering analyses, creating and modifying 3D CAD models and technical drawings, reviewing industry codes and standards, and identifying process enhancements for continuous improvement. You will also collaborate with Sales Engineers, multi-functional teams, and global engineering teams to ensure smooth project execution. To be successful in this role, you should have a Bachelor or Master's degree in Engineering (Mechanical, Materials, Industrial, Chemical, Design, or Aerospace), along with 3-5 years of experience in Flow Controls or a similar field in the valve industry. You should have a solid understanding of engineering principles, materials properties, castings, forgings, machining, welding, industry codes, and standards. Additionally, you should be capable of working on multiple tasks accurately and efficiently. At Emerson, we prioritize a workplace where every employee is valued, respected, and empowered to grow. We foster an environment that encourages innovation, collaboration, and diverse perspectives. Our commitment to ongoing career development and growing an inclusive culture ensures you have the support to thrive. We offer competitive benefits plans, medical insurance, employee assistance programs, recognition, and flexible time off plans. Emerson is a global leader in automation technology and software, helping customers in critical industries operate more sustainably while improving productivity and reliability. We offer equitable opportunities, celebrate diversity, and embrace challenges with confidence. Join our team and make a difference with Emerson.,

Your Role and Responsibilities Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. . Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 4 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Nice to haves -Knowledge of verification principles and coverage. -Knowledge of test generation tools and working with ISA reference model. -Experience with translating ISA specifications to testplan. -Understanding of Agile development processes. -Experience with DevOps design methodologies and tools. Preferred technical and professional experience Work with Hiring Manager to ID up to 3 bullets max (encouraging then to focus on required skills) Advanced Verification Techniques: Familiarity with advanced verification techniques such as RAS verification is a plus Experience with Hardware Description Languages (HDLs): Proficiency in hardware description languages like Verilog and VHDL, enabling seamless collaboration with design teams and enhancing verification effectiveness. Experience in System-Level Verification: Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design abstraction.

Your Role and Responsibilities Lead the unit level pre-silicon functional & performance verification the Instruction Sequencing Unit for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for ISU which covers the Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of Instruction Dispatch verification. Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying Load Store unit of any CPU architecture. Hands on experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling etc. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic units. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

Your Role and Responsibilities Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Required Technical and Professional Expertise 8 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic unit. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

Conduct on-site inspections, audits and assessments to ensure compliance with industry standards and client specs. Document findings, prepare detailed reports and coordinate with clients and internal teams for effective quality assurance. Required Candidate profile Willingness to travel extensively. Good understanding of electrical systems, instrumentation principles & basic testing procedures. Strong report writing, documentation, and communication skills.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: CPU architecture team is driving the core math libraries needed for ML/AI acceleration. This position/s will expose you to Qualcomms cutting edge SoC and ML/AI platforms in the industry. Participate in Optimizing the core ML kernels using the latest advancements like SME, SVE of the ARM CPU architecture and enhance the performance of the ML models on the CPU of the QCOM Soc Required Skills== 7+ experince with Understanding of ARM CPU architecture fundamentals and ARM Arch64 ISA Optimizing kernels for vector Processors Understanding of the basic linear algebra functions used in AI/ML Algorithm design (logic, critical thinking) Performance Evaluation and Optimization of the applications for ARM architecture Inferencing of the ML models written in Pytorch/TensorFlow/Keras Understanding of the typical Open-Source Library framework design Preferred Skills=== Strong Programming skills and deep understanding of the ARM ISA understanding of the algorithms suitable for Vector and matrix accelerators Strong Analytical and debugging skills Good understanding of Optimizing the Linear Algebra algorithms Performance evaluation using QEMU, Simulators, Emulators and on Real Hardware Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. 2+ years of work experience with Programming Language such as C, C++, Java, Python, etc. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As a fast-growing multinational chartered accountancy firm in Kolkata, we are looking for a Qualified Chartered Accountant with expertise in audit and team leadership to join our international division. Your responsibilities will include managing External Audits and Finalization of Accounts, supporting the audit operations team, and utilizing your knowledge of IFRS/IND-AS and ISA/SA. To excel in this role, you must have prior experience in a CA firm, possess a CA qualification with at least 13 years of relevant experience, and demonstrate a strong understanding of accounting standards, Auditing Standards, and proficiency in MS Office. Additionally, we value candidates with excellent analytical, communication, and teamwork skills. In return, we offer exciting opportunities for international exposure and career growth, a supportive and respectful work culture, and the chance for all-round skill development. This is a Full-Time position based in Kolkata. If you meet the requirements and are ready to take on this challenging yet rewarding opportunity, please get in touch with us at 7761821500 or via email at annu@rtulsian.com.,

Application Deadline: 11 August 2025 Department: Instrumentation Controls Employment Type: Full Time Location: Pune, MH, India Description Equinox Engineering Ltd., a leading EPCM firm headquartered in Calgary, specializes in oil and gas processing, providing comprehensive services in facilities design, implementation, and operational support for natural gas, conventional, and heavy oil projects. Our clientele includes major oil and gas producers in Canada and globally, and we are actively engaged in diverse sweet gas, sour gas, conventional oil, heavy oil facility, and pipeline projects. Job Overview: Instrumentation and control engineers work on measuring and controlling instrumentation. They also service plant process control, monitoring, safety and communications systems. They are knowledgeable in overall plant systems and interactions of processes. Key Responsibilities Create Instrumentation & Automation engineering documentation including datasheets, P&IDs, control narratives, instrument indexes, control specifications and installation design details. (Knowledge and experience applying codes and standards such as CSA, API, ANSI and ISA would be an asset). Knowledge of various electrical components including MCCs, PLC equipment panels and motors. Review engineering and construction work packages for content accuracy and quality standards. Review vendor and shop drawings for design compliance. Prepare engineering QC document as per company and client standards. Provide and demonstrate leadership in accordance with Environment Health and Safety program to establishing a strong safety culture within the organization and ensure compliance with health and safety regulations and quality standards. Assist in selection of discipline personnel assigned to projects. Monitor/supervise the work of junior executors and assist with mentorship and training. Interface with the other engineering disciplines to ensure a coordinated design and that project engineering deliverables are completed. Direct and/or participate in job site visits to collect or deliver design and engineering data. Direct and/or participate in vendor drawings reviews to ensure design accuracy and compliance with specifications. Direct and/or participate in inspections/testing of instrumentation systems/ vendor skid packages. Design, configuration, integration and implementation of process control solutions. Assemble bid, approval, and construction issue drawing packages. Key Skills and Abilities Specify and purchase field instruments including electronic and pneumatic transmitters, switches, meter-runs, analyzers, control valves and ESD valves. Excellent computer skills including use of engineering and computer software to complete control valve, PSV and flow meter sizing. Knowledge and experience applying codes and standards such as CSA, API, ANSI and ISA. Proficient in the use of Smart Plant Instrumentation (Intools) software. Requires a broad knowledge of the application of engineering to plant constructability as applied to construction methods and materials, and the economics involved. Experience in Oil & Gas facility projects including some of the following areas: heavy oil facilities, well tie-ins, pipelines, compressor stations, and field gas processing facilities. Education and Qualifications: Degree in Instrumentation Engineering. 5+ years oil & gas experience, preference for an EPCM background. Our People and Culture: Flexible Work Schedules for a healthy work-life integration. Abundant growth opportunities, mentorship programs, and continuous learning initiatives. Our Environmental Commitment: Equinox believes in a balanced energy future. Our projects, from Carbon Capture and Sequestration to Renewable Natural Gas, exemplify our commitment to an environmentally responsible energy sector. Equinox Success Statement: Equinox consistently delivers focused and experienced premium teams, custom-tailored with the best technical expertise to align seamlessly with client culture and requirements. Our commitment ensures the successful execution of projects on a repeatable basis.

As an Audit Quality Assurance Associate, you will be responsible for reviewing client financial statements to ensure compliance with accounting and auditing standards. Your role will involve identifying discrepancies, errors, and areas for improvement in audit documentation. Additionally, you will work on maintaining audit quality and compliance by following firm-wide policies, procedures, and standards. Your assistance will be valuable in implementing updates to audit methodologies and best practices. Furthermore, you will play a crucial role in supporting training and development initiatives by contributing to the development of training materials and conducting audit-related training sessions. Your guidance to audit teams on technical issues and industry standards will be essential for their professional growth. It will also be your responsibility to stay updated with IFRS, ISA, and other regulatory changes to support the implementation of new quality control procedures within the firm. In this role, you will be expected to identify gaps in the audit process and propose improvements to enhance efficiency and documentation quality. Collaboration with audit teams will be key to implementing these improvements effectively. To qualify for this position, you should hold a CA, CPA, ACCA, or equivalent qualification, along with 2-5 years of experience in external audit, financial reporting, or audit quality review. Experience with Big 4 or mid-tier audit firms would be advantageous. Your technical skills should include a strong understanding of IFRS and ISA, while your soft skills should encompass attention to detail, strong analytical abilities, and excellent communication skills for effective interaction with engagement teams. If you are looking to join a dynamic team in Ahmedabad and contribute to ensuring audit quality and compliance, this role may be the perfect fit for you.,

SPI ADMIN 5 and above years of experience, hands-on exp on SPI. Preferred Eng graduates. Diploma will be ok Key Responsibilities Database Management : Create, configure, and maintain SPI project databases; manage data merging, backups, and archival. User & Access Control : Assign user roles, manage permissions, and support global SPI users. Loop & Wiring Diagrams : Oversee generation and QA of loop drawings, JB schedules, and wiring diagrams. Data Integrity & QA/QC : Perform quality checks on SPI data against P&IDs, datasheets, and engineering standards. Project Support : Collaborate with engineering, maintenance, and operations teams to support instrumentation deliverables. As-Built Updates : Incorporate plant changes and project modifications into SPI with accurate documentation. Template & Symbol Management : Customize SPI templates, symbols, and reports to meet project-specific needs. System Integration : Interface SPI with other tools like SmartPlant Foundation, SAP, and CAD platforms. Skills & Qualifications Proficiency in SPI/INtools (v2007 or later) Strong understanding of instrumentation systems (field instruments, control valves, DCS/PLC) Familiarity with ISA standards , P&IDs, and instrument datasheets Experience with CAD tools , GSAP , and Microsoft Office Degree/Diploma in Instrumentation, Electronics, or Electrical Engineering Additional Knowledge of SQL , SmartSketch , or Lean CI methodology Preferred candidate profile Immediate Joiners Prior work exp in the same field is must Interested candidates share your resume on the given mail id hr@prvaa.com to schedule your interviews right away!!

5 and above years of experience, hands-on exp on SPI. Preferred Eng graduates. Diploma will be ok Key Responsibilities Instrument Index & Datasheets : Create and manage instrument index, process datasheets, and specification sheets using SPI. Loop & Wiring Diagrams : Generate loop diagrams, wiring diagrams, and interconnection drawings for conventional and fieldbus instruments. P&ID Integration : Interpret and extract data from P&IDs to populate SPI modules accurately. Hook-Up Drawings : Prepare and review instrument hook-up drawings and mounting details. Cable Scheduling : Develop cable schedules and junction box (JB) layouts. Database Management : Maintain SPI database integrity, perform data merging, and manage templates and symbol libraries. QA/QC & As-Built Updates : Conduct quality checks, update SPI with as-built data, and ensure compliance with project standards. Cross-Discipline Coordination : Collaborate with electrical, piping, and control teams to ensure instrumentation integration. Skills Proficiency in SPI/INtools (all modules) Strong grasp of instrumentation standards (ISA, IEC, IS) Familiarity with control systems (PLC, DCS, marshalling panels) Experience with CAD tools (AutoCAD or SmartSketch) Good understanding of engineering deliverables and documentation workflows Preferred candidate profile Hands-on exp on SPI Immediate Joiners Interested candidates please share resumes on hr@prvaa.com to schedule your interview!!

Lead the unit level pre-silicon functional & performance verification of the front end of the pipeline for our next -generation IBM POWER processor core systems offering. Architect and enhance the existing verification environment for Instruction fetch, Branch Prediction and Instruction Decode units of the high performance processor CPU. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12 years or more experience in functional verification of processors, demonstrating a deep understanding of core units (eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) Good understanding of computer architecture, including Processor core design specifications, with expertise in verifying frontend pipeline units of any CPU architecture. Hands on experience of Branch Prediction techniques. Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA Experience with high frequency, instruction pipeline designs At least 1 generation of Processor Core silicon bring up experience In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of instruction dispatch and Arithmetic unit. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Knowledge of verification principles and coverage. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of verification principles and coverage. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

About Gradiant Gradiant is a global solutions provider for advanced water and wastewater treatment. Founded at MIT and headquartered in Boston, we design and build innovative, end-to-end systems that reduce water usage, recover valuable resources, and transform wastewater into freshwater. Our Coimbatore team supports international projects, driving sustainability across critical industries. Role Overview We are seeking a Lead Instrumentation & Control Engineer to drive the design and engineering of instrumentation systems for global water and wastewater treatment facilities with a primary focus on USA projects. This role is office-based in Coimbatore and requires strong engineering deliverables experience , collaboration across disciplines, and minimal site involvement. Key Responsibilities Lead instrumentation and control (I&C) design engineering for international water and wastewater treatment projects. Review and develop P&IDs , instrument index , and I/O lists in coordination with process engineers. Prepare and review: Datasheets , RFQs , TQs , and TBEs for field instruments including: Pressure / Temperature Gauges and Transmitters Flow Meters (Orifice, Magnetic, Ultrasonic) Level Gauges / Transmitters, PSV Control Valves, On-Off Valves PLCs, DCS, ESD Systems Hookup drawings , cable block diagrams , cable schedules , JB interconnection drawings , installation drawings Contribute to IDC (Interdisciplinary Checks) with other disciplines (Mechanical, Civil, Electrical, Process). Provide instrument load data to Structural/Civil for layout planning. Conduct 3D model reviews in Navisworks for instrument layout, cable routing, and installation clearance. Support in vendor selection , document reviews , and FAT participation when required. Ensure compliance with international standards like ISA, IEC, NEC throughout the engineering lifecycle. Required Qualifications Bachelor’s Degree in Instrumentation Engineering or equivalent. Minimum 10 years of I&C design engineering experience, with at least 3 years in a lead role . Proven experience in detailed design of: Skid-based / modular / stick-built treatment systems Instrument selection, sizing, loop design, and control logic development Experience with engineering tools : AutoCAD, EPLAN, SPI (INtools), Excel, Navisworks. Excellent coordination skills with cross-discipline teams. Familiarity with water/wastewater or EPC projects in energy, oil & gas, or utilities . Preferred (Nice to Have) Exposure to USA project specifications and standards. Knowledge of safety instrumented systems , cause & effect matrix , loop diagrams . Understanding of SCADA/PLC architecture design from an engineering point of view.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: CPU architecture team is driving the core math libraries needed for ML/AI acceleration. This position/s will expose you to Qualcomm’s cutting edge SoC and ML/AI platforms in the industry. Participate in Optimizing the core ML kernels using the latest advancements like SME, SVE of the ARM CPU architecture and enhance the performance of the ML models on the CPU of the QCOM Soc Required Skills== 3+ experince with Understanding of ARM CPU architecture fundamentals and ARM Arch64 ISA Optimizing kernels for vector Processors Understanding of the basic linear algebra functions used in AI/ML Algorithm design (logic, critical thinking) Performance Evaluation and Optimization of the applications for ARM architecture Inferencing of the ML models written in Pytorch/TensorFlow/Keras Understanding of the typical Open-Source Library framework design Preferred Skills=== Strong Programming skills and deep understanding of the ARM ISA understanding of the algorithms suitable for Vector and matrix accelerators Strong Analytical and debugging skills Good understanding of Optimizing the Linear Algebra algorithms Performance evaluation using QEMU, Simulators, Emulators and on Real Hardware Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc.

Job Area: Engineering Group, Engineering Group > Machine Learning Engineering General Summary: CPU architecture team is driving the core math libraries needed for ML/AI acceleration. This position/s will expose you to Qualcomm’s cutting edge SoC and ML/AI platforms in the industry. Participate in Optimizing the core ML kernels using the latest advancements like SME, SVE of the ARM CPU architecture and enhance the performance of the ML models on the CPU of the QCOM Soc Required Skills== 7+ experince with Understanding of ARM CPU architecture fundamentals and ARM Arch64 ISA Optimizing kernels for vector Processors Understanding of the basic linear algebra functions used in AI/ML Algorithm design (logic, critical thinking) Performance Evaluation and Optimization of the applications for ARM architecture Inferencing of the ML models written in Pytorch/TensorFlow/Keras Understanding of the typical Open-Source Library framework design Preferred Skills=== Strong Programming skills and deep understanding of the ARM ISA understanding of the algorithms suitable for Vector and matrix accelerators Strong Analytical and debugging skills Good understanding of Optimizing the Linear Algebra algorithms Performance evaluation using QEMU, Simulators, Emulators and on Real Hardware Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. 2+ years of work experience with Programming Language such as C, C++, Java, Python, etc.

Job Description: Stantec is a leader in global infrastructure, water resource development and works in the Buildings, Mining and Oil and Gas sectors providing engineering design and remediation, program management and technology solutions for the environmental, water, wastewater, energy and power markets of the North Americas, Europe, Middle East and Asia Pacific regions. Stantec is lookingfor Electrical (Electrical, ICT/ELV) Designer with MEP expertise in Buildings sector with following capabilities and experience to be based in the Pune, India office. Responsibilities: Prepare of Electrical equipment layout and plans Prepare Cable schedule, cable route diagrams and conduit development Prepare ref. MCC and control Panel Elevation drawings and GAs Prepare Load schedules and Single Line diagrams Prepare Earthing and Lighting layout drawings Update Project website for latest information Coordination with Civil / Mech / Process and other disciplines Communicate with global internal clients for input information and project status Carry out other duties as may be assigned from time to time by supervisor/management. and reinforces all branding and talent brand. Stantec is a global leader in sustainable engineering, architecture, and environmental consulting. The diverse perspectives of our partners and interested parties drive us to think beyond what s previously been done on critical issues like climate change, digital transformation, and future-proofing our cities and infrastructure. We innovate at the intersection of community, creativity, and client relationships to advance communities everywhere, so that together we can redefine what s possible. The Stantec community unites approximately 32,000 employees working in over 450 locations across 6 continents. Qualifications and Experience: BE / Diploma in Electrical 3-8 years of experience Building projects experience minimum 2 years. Must have experience working on REVIT, AutoCAD, Bentley MicroStation and Navisworks. Experience working in remote / virtual environment, WTP and pump station and using AutoCAD Electrical, Revit MEP, BIM360 etc. will be an added advantage. Experience using Microsoft Office Suite (Word, Excel etc.), Knowledge of AS/NZS standards Knowledge of other international standards like NEC, ISA, BS, IEC, NEMA will be added advantage. Good Communication skills, presentation skills, learning attitude, good grasping power and a good team member.

Lead the architecture, design and development of a server class, high- performance Processor CPU for IBM Systems. - Architect and design Instruction caches, Branch Predictors, Issue queues, Register Renaming, Load Store Execution and other areas of the IBM processor CPU - Research novel instruction/data prefetching and branch prediction architectures. - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

- Lead the architecture, design and development of Instruction Sequencing Unit for high-performance Processor CPU of IBM Systems. - Architect and design Instruction Dispatch to Issue queues, Register Renaming for Out of Order Execution, Issue instructions to Execution Pipelines, Reordering Buffers for completion of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8 or more years of demonstrated experience in architecting and designing Instruction Dispatch unit of CPU - Hands of experience of implementing Issue Queues, Register renaming and forwarding, Reordering Buffer and Pipeline flush/exception handling - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of Instruction Decode and Execution units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

Lead the architecture, design and development of Processor Core Front end of pipeline units for high-performance IBM Systems. - Architect and design I-Cache, Instruction Fetch, Branch Prediction and Decode units of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise .12 or more years of demonstrated experience in architecting and designing specific CPU unit(eg. I-Cache, Instruction Fetch, Branch Prediction, Instruction Decode) - Hands on experience of different Branch Prediction techniques - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Knowledge of at least one object oriented or functional programming language and scripting language. - Nice to haves - Knowledge of instruction decode and handling pipeline hazards - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Lead the architecture, design and development of a server class, high- performance Processor CPU for IBM Systems. - Architect and design Instruction caches, Branch Predictors, Issue queues, Register Renaming, Load Store Execution and other areas of the IBM processor CPU - Research novel instruction/data prefetching and branch prediction architectures. - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise Expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of object oriented languages and scripting languages - Understanding of Agile development processes - Experience with DevOps design methodologies and tools

Lead the architecture, design and development of Processor Core Vector- Scalar Execution unit for high-performance IBM Systems. - Architect and design Fixed point/Floating point/Vector/SIMD/Crypto instructions of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise 12 or more years of demonstrated experience in architecting and designing Execution unit of CPU - Hands on experience of implementing Arithmetic/Crypto/SIMD functions - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and load/store units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.

Lead the architecture, design and development of Processor Core Load- Store Execution unit for high-performance IBM Systems. - Architect and design Load and Store pipelines, D-Cache, Address Translation, Out of Order Execution of a high performance processor CPU - Develop the features, present the proposed architecture in the High level design discussions - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature. - Develop micro-architecture, Design RTL, Collaborate with other Core units, Verification, DFT, Physical design, Timing, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in post silicon lab bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. Required education Bachelor's Degree Preferred education Doctorate Degree Required technical and professional expertise 12 or more years of demonstrated experience in architecting and designing Load-Store Execution unit of CPU - Hands on experience of implementing D-Cache, Address Translation, Memory Consistency handling, Store ordering etc. - Deep expertise in Out of Order, Super Scalar, Multi-Threaded Core Architecture and ISA - Experience with high frequency, instruction pipeline designs - At least 1 generation of Processor Core silicon bring up experience - In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) - Proficiency of RTL design with Verilog or VHDL - Nice to haves - Knowledge of instruction dispatch and Arithmetic units - Knowledge of verification principles and coverage - High-level knowledge of Linux operating system - Knowledge of one object oriented language and scripting language - Understanding of Agile development processes - Experience with DevOps design methodologies and tools Preferred Education

Choosing Capgemini means choosing a company where you will be empowered to shape your career in the way you’d like, where you’ll be supported and inspired bya collaborative community of colleagues around the world, and where you’ll be able to reimagine what’s possible. Join us and help the world’s leading organizationsunlock the value of technology and build a more sustainable, more inclusive world. Your Role Minimum 3-8 years’ experience assessing against standards and frameworks including one or more of the followingDOE C2M2, IEC-62243/ISA-99, NIST CSF, NERC CIP, etc. Minimum 3-5 years’ experience working with ICS technologies and/or environments on one or more of the followingSCADA, DCS, EMS, DMS, ADMS, PCN, RTUs, IACS, PLCs, HMIs, etc. Minimum 3-5 years working with cybersecurity functions of one or more of the followingvulnerability assessment and management processes, identity and access management, incident response and monitoring, etc. Problem-solving ability and strong analytical skills Experience of working with diverse teams and is a team player Relevant certifications (CISSP, GICSP, GRID, GCIP, etc.). Keep abreast with the latest technology trends and predictions Ability to drive the creation of prototypes and proof of concepts Able to effectively communicate, interact and influence business and operational stakeholders and partners Ability to deliver innovative solutions and consistently demonstrate customer outcomes. Primary Skills DOE C2M2 IEC-62243/ISA-99 NIST CSF NERC CIP