13 Ip Integration Jobs

You are an experienced RTL/FPGA Design Engineer with a minimum of 3 - 7 years of experience in the VLSI domain. You hold a BE/B.Tech degree in Electronics/Electronics & Communication or ME/M.Tech in Electronics/VLSI Design or a closely related field from a recognized university with a strong academic background. Your role will be based in Ahmedabad or Bangalore. In this role, you will be responsible for RTL programming using Verilog/System Verilog or VHDL, possessing knowledge of the complete FPGA Design Development flow. You should be proficient with FPGA Development Tools such as Quartus, Modelsim, Vivado, Xilinx ISE, Libero, etc. Additionally, you will engage in functional verification using Verilog/System Verilog or VHDL, optimize RTL code to meet timings and on-chip resources, and support all phases of FPGA-based product development activities. System Architecture Design, testing, and troubleshooting of hardware will also be part of your responsibilities. To excel in this position, you must have experience with Verilog/SystemVerilog or VHDL for design and verification, along with a deep understanding of FPGA design flow/methodology, IP integration, and design collateral. You should be capable of developing small IP blocks from scratch and conducting basic functional verification. Familiarity with protocols like SPI, I2C, UART, and AXI, as well as knowledge of Altera Quartus II Tool, Questasim, Modelsim, Xilinx tools like ISE and Vivado, and Microsemi tools like Libero, are essential. Understanding of USB, Ethernet, and external memories such as DDR, QDR RAM, and QSPI-NOR based Flash is also required. In terms of personal competencies, you should be self-motivated to learn and contribute, able to work effectively with global teams, and willing to collaborate in a team-oriented environment. Prioritization and execution of tasks to achieve goals in a fast-paced environment, along with strong problem-solving skills, are valuable assets. Your passion for writing clean and neat code that aligns with coding guidelines will be highly appreciated. If you meet these qualifications and are excited about the opportunity to work in the VLSI domain as an RTL/FPGA Design Engineer, we encourage you to apply now.,

You have an exciting opportunity to join a dynamic team at MarvyLogic in Bengaluru/Bangalore. With over 10 years of experience in ASIC RTL Design and a Graduate Degree in Electrical/Electronics Engineering (Post Graduate degree is a plus), you will be a valuable addition to our team. As a member of our team, you will be responsible for various tasks related to ASIC RTL Design. Your expertise in Verilog/System Verilog proficiency, experience with multiple clock and power domains, and integration and validation of high-speed PCIe IP core will be crucial. You will also need familiarity with PCIe protocol analyzers and debug, as well as PCIe driver and application software for Linux/Windows. Your role will involve RTL Design and implementation of interface logic between PCIe controller and DMA engines for high-performance networking applications. You will be creating block-level micro-architecture specifications, reviewing vendor IP integration guidelines, and running integrity check tools to ensure compliance throughout the design flow. In addition to your technical responsibilities, you will also need to work and communicate effectively with multi-site teams. Your experience in ASIC product life cycle, including requirements, design, implementation, test, and post-silicon validation, will be essential in this role. If you are passionate about technology solutions and enjoy working in a collaborative environment, we encourage you to apply for this position. Join us at MarvyLogic and be a part of building futuristic and impactful solutions that make a difference in various industries. Your experience with emerging technologies and your contributions to our team may help you evolve both professionally and personally, leading to a more fulfilling life.,

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by utilizing your skills and expertise. You will be responsible for hands-on layout experience in various analog IP components such as Opamps, Bandgaps, Data converters, LDO, PLL, and more. Your role will involve understanding the impact of layout on the circuit regarding speed, capacitance, power, and area. Knowledge of analog layout techniques like matching, shielding, and familiarity with DSM technology methodology will be essential. Experience with the latest technology nodes, specifically 28nm and below, is preferred. Additionally, you will be expected to possess good communication skills, work effectively as a team player, and have experience with scripting and automation. High-speed analog layout experience in areas like Serdes, power management, and PLL will be beneficial. Understanding layout effects on the circuit and various techniques, floorplan constraints, and IP integration at the chip level will be part of your responsibilities. Qualifications for this role include a degree in BE/BTech/ME/MS/MTech in Electrical/Electronics. Strong written, verbal, and presentation skills are essential, along with the ability to establish close working relationships with customers and management. You should exhibit strong analytical and problem-solving skills and be open to exploring unconventional solutions to get the job done. Operating with integrity and pushing to raise the bar will be key aspects of your role. Join us in our mission to tackle challenges that others cannot solve and be a part of work that truly matters at Cadence.,

As an RTL/FPGA Design Engineer in the VLSI domain, you will play a crucial role in developing FPGA-based products. With a focus on RTL programming using Verilog/System Verilog or VHDL, you will be responsible for optimizing RTL code to meet timing requirements and on-chip resource constraints. Your expertise in FPGA Development Tools such as Quartus, Modelsim, Vivado, Xilinx ISE, and Libero will be essential in ensuring the successful completion of projects. Your responsibilities will include functional verification using Verilog/System Verilog or VHDL, system architecture design, and testing/troubleshooting of hardware components. Additionally, you will be required to support all phases of FPGA-based product development activities, demonstrating a strong understanding of FPGA design flow/methodology and IP integration. To excel in this role, you should hold a BE/B.Tech or ME/M.Tech degree in Electronics/Electronics & Communication or Electronics/VLSI Design from a recognized university. Proficiency in Verilog/SystemVerilog or VHDL for design and verification is essential, along with knowledge of protocols like SPI, I2C, UART, and AXI. Familiarity with tools such as Quartus II, Questasim, Modelsim, ISE, Vivado, and libero will be advantageous. As a self-motivated individual, you should be eager to learn and contribute effectively within a team-oriented environment. Your ability to prioritize tasks, solve problems creatively, and write clean code following coding guidelines will be highly valued. If you are passionate about working in a dynamic and innovative setting, we encourage you to apply for this exciting opportunity in Ahmedabad or Bangalore. Join us and be a part of our vibrant team dedicated to pushing the boundaries of VLSI design and FPGA technology. Apply now to explore this role further and take the next step in your career growth.,

As an FPGA Firmware Engineer, you will be responsible for developing detailed specifications based on requirements and implementing FPGA designs in accordance with those defined requirements and/or specifications. You will collaborate with other members of the design team to evaluate possible alternatives during the development process and determine the best approach based on performance, cost, and resources. Additionally, you will perform simulation activities including timing analysis, behavioral, and functional simulations. Your role will also involve documenting ideas, designs, specifications, and instructions to comply with client standards. As a senior member of the team, you will mentor junior members of the business unit to promote design team abilities and establish good working practices. The ideal candidate should possess a degree in Computer Science, Engineering, or a related field such as Electronics, Electrical, Computer Engineering, or Computer Science Engineering. You should have 5-10 years of experience in FPGA design, FPGA firmware, or related work. Excellent interpersonal and analytical skills are essential, with the ability to work independently and create customer-facing applications. Preferred expertise for this role includes 5+ years of direct hands-on experience with IP integration and/or HLS based implementation for resources and timing optimization. Good interpersonal skills are a must, as you will be required to work between multiple departments in carrying out the duties of this position.,

You will be joining Synopsys, a company at the forefront of technological innovations that are shaping the way we live and connect in the Era of Pervasive Intelligence. Synopsys leads in TCAD, chip design, verification, and IP integration, enabling the development of high-performance silicon chips and software content. As part of this dynamic environment, you will have the opportunity to contribute to continuous technological innovation. As a highly skilled and knowledgeable professional with a deep passion for semiconductor physics and technology, you should hold a PhD or MS degree in Electrical Engineering, Physics, or Materials Sciences. Your expertise in semiconductor devices and process technologies, along with a profound understanding of semiconductor manufacturing processes and process modeling, will be instrumental in your role. Your ability to analyze and interpret experimental test/characterization data, coupled with excellent presentation and communication skills, will facilitate effective interaction across teams and organizational levels. In this role, you will be responsible for conducting TCAD calibration projects for advanced logic and memory technologies, providing consulting services to customers to enhance the value of TCAD, and collaborating with R&D, sales, marketing, and customers to drive product development and acceptance. Additionally, you will manage customer projects from definition to execution and follow-up. Your contributions will have a significant impact on improving the quality and functionality of TCAD tools, driving the successful adoption of TCAD products in customer projects, and contributing to product development through feedback and collaborative efforts with R&D teams. By fostering strong customer relationships, you will enhance Synopsys" market position as a leader in semiconductor technology and simulation tools. To excel in this role, you should possess a PhD degree in Electrical Engineering, Physics, Materials Sciences, or a related field, along with 5+ years of industry or research experience. Advanced knowledge and experience in semiconductor process technology, device design based on Silicon, and hands-on experience with TCAD simulation tools are essential. A strong understanding of semiconductor devices physics and proficiency in Python scripting would be advantageous. As a collaborative team player with a "help others succeed" mentality, you should be detail-oriented with strong problem-solving abilities, adaptable to fast-paced environments, proactive, self-motivated, and passionate about continuous learning and improvement. Your ability to interact effectively at both engineering and management levels within customer organizations will be key to your success. You will be part of the Product Application Engineering team within TCAD R&D, working on market-leading solutions and services for TCAD and EDA. Your role will involve driving the successful adoption of technologies and platforms at a diverse set of customers and partners across various market segments.,

KEY RESPONSIBILITIES: Define and drive key Frontend/Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details.

KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 7+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ? ACADEMIC CREDENTIALS: ? Bachelors orMastersdegree in computer engineering/Electrical Engineering

As a member of the Common Hardware Group (CHG) at Cisco, you will be part of a team that delivers cutting-edge silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Our work involves designing networking hardware for Enterprises, Service Providers, Public Sector, and Non-Profit Organizations worldwide. Join us in shaping Cisco's groundbreaking solutions by participating in the design, development, and testing of advanced ASICs that are at the forefront of the industry. Your role will involve implementing Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug, and diagnostics requirements of the designs. You will collaborate with multi-functional teams to develop innovative DFT IP and play a crucial role in integrating testability features in the RTL. Working closely with design and PD teams, you will ensure the seamless integration and validation of test logic throughout all phases of implementation and post-silicon validation flows. Your team will contribute to the creation of innovative Hardware DFT and physical design aspects for new silicon device models, bare die, and stacked die. You will drive re-usable test and debug strategies while showcasing your ability to craft solutions and debug with minimal mentorship. To excel in this role, you are required to have a Bachelor's or Master's Degree in Electrical or Computer Engineering along with a minimum of 10 years of relevant experience. Your expertise should encompass knowledge of the latest trends in DFT, test, and silicon engineering. Proficiency in Jtag protocols, Scan and BIST architectures, ATPG, EDA tools, and verification skills like System Verilog Logic Equivalency checking will be essential. Preferred qualifications include experience in Verilog design, DFT CAD development, Test Static Timing Analysis, and Post-silicon validation using DFT patterns. Your background in developing custom DFT logic and IP integration, familiarity with functional verification, and scripting skills like Tcl, Python, or Perl will be advantageous. At Cisco, we value diversity, innovation, and collaboration. We empower our employees to bring their unique talents to work, driving positive change and powering an inclusive future for all. As a company that embraces digital transformation, we encourage creativity, innovation, and a culture that supports learning and growth. Join us at Cisco, where every individual is valued for their contributions, and together, we make a difference in the world of technology and networking.,

Roles & Responsibilities: Lead the verification planning and execution for complex SoC designs. Define and implement testbenches using SystemVerilog/UVM methodologies. Work closely with architecture, design, and firmware teams to understand the design and develop test strategies. Drive block-level and full-chip verification , including IP integration . Perform coverage analysis , debug , and triage failures . Develop and maintain automation scripts to improve verification workflows. Mentor and guide junior verification engineers and drive best practices across the team. Ensure delivery on schedule with high quality and coverage metrics.

Minimum qualifications: You should hold a Bachelor's degree in Electrical Engineering, a related field, or possess equivalent practical experience. Additionally, you must have at least 5 years of experience in DFT specification definition architecture and insertion. A minimum of 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent) is required. Your background should also include experience with ASIC DFT synthesis, STA, simulation, and verification flow. It is essential to have experience collaborating with ATE engineers, involving tasks such as silicon bring-up, patterns generation, debug, validation on automatic test equipment, and resolution of silicon issues. Preferred qualifications: A Master's degree in Electrical Engineering or a related field would be advantageous. Moreover, experience in IP integration (e.g., memories, test controllers, TAP, and MBIST), SoC cycles, silicon bring-up, and silicon debug activities, as well as fault modeling, would be beneficial for this role. About the job: Join a forward-thinking team dedicated to developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a vital role in the innovation process behind products cherished by millions globally. As part of this role, you will be tasked with defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. Responsibilities include defining silicon test strategies, DFT architecture, creating DFT specifications for next-generation SoCs, designing, inserting, and verifying the DFT logic, and collaborating with test engineers. Your role will focus on reducing test costs, improving production quality, and enhancing yield. Responsibilities: Your responsibilities will involve developing DFT strategy and architecture, encompassing hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. You will demonstrate ownership from DFT logic development and pre-silicon verification to collaboration with test engineers post silicon. Additionally, you will insert various DFT logic components, such as boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, and Clock Control block. Furthermore, you will be responsible for inserting and connecting MBIST logic components, documenting DFT architecture and test sequences, and ensuring compliance with Test Design Rule Checks (TDRC) to achieve high test quality and support the post-silicon test team effectively.,

Contribute to modeling, integration, and testing of various peripherals in SystemC-based platform modeling framework Understand IP modeling requirements and generate ESL model specifications Resolve technical issues related to IP modeling and platform integration Guide junior engineers and consultants on SoC platform creation and validation Support software bring-up and debug platform integration issues Collaborate with cross-functional teams to ensure successful execution and delivery The Impact You Will Have: Advance platform modeling and integration of high-performance silicon chips Improve efficiency and scalability of SystemC-based frameworks across domains like Automotive and Wireless Ensure accurate and functional SoC platform creation and validation Provide mentorship and technical leadership to junior engineers Deliver high-quality modeling solutions that align with Synopsys innovation goals Enable successful deployment of next-gen technologies through robust platform models What You'll Need: Bachelor's or Master's in Electrical Engineering or Computer Science 6+ years of industry experience Strong proficiency in C++, SystemC/TLM modeling Solid understanding of bus/memory architectures and SoC interfaces Familiarity with protocols such as IEEE 802.3 Ethernet, PCIe (preferred) Experience in modeling SoC peripherals using C++/SystemC/HDL (preferred) Knowledge of AMBA, AXI, OCP, or NoC protocols (preferred) Exposure to assembly or high-level application development and multicore platforms (preferred)

Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Your role and responsibilities We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design . Experience working with ATE engineers for silicon bring up, silicon debug and validation. . Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.