DFT Design Engineer - Foundry Team Samsung Electronics

5.0 - 9.0 years

0 Lacs

karnataka

On-site

The position available involves working with Samsung Semiconductor India Research (SSIR), an innovative hub focused on developing cutting-edge semiconductor solutions. As part of one of the largest R&D centers for Samsung Electronics outside Korea, you will have the opportunity to work on advanced technologies in System LSI, Memory, Foundry, and more. Your role will entail collaborating on diverse projects, conducting research in emerging technology areas, and contributing to the development of world-class products. We are seeking a professional with over 5 years of experience in full chip Design for Testability (DFT) architecture, implementation, timing closure, and post-silicon validation. Your expertise should cover areas such as scan architecture planning, MBIST architecture, analog and mixed-signal IP testing, and timing closure for various test modes. You should be adept at leading a team, coordinating with RTL and physical design teams, and managing project timelines effectively. The ideal candidate will hold a B.Tech/B.E/M.Tech/M.E degree with a strong background in DFT methodologies. Knowledge of JTAG operation, iJTAG protocol, and functional testing is essential for this role. Additionally, you should have a proactive approach to identifying risks, troubleshooting timing issues, and ensuring high reliability and performance in semiconductor testing. Samsung Semiconductor India Research (SSIR) is committed to fostering a diverse and inclusive work environment, offering Equal Employment Opportunity to all individuals. Regardless of your background, SSIR values creativity, innovation, and a collaborative spirit in driving technological advancements. If you meet the qualifications and are excited about working on cutting-edge technologies with a global leader in semiconductor solutions, we encourage you to apply for this challenging and rewarding opportunity.,

Posted 4 days ago

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Design Engineer Samsung Electronics

5.0 - 9.0 years

0 Lacs

karnataka

On-site

The position at Samsung Semiconductor India Research (SSIR) requires a Senior DFT Engineer with at least 5 years of experience in full chip DFT architecture, implementation, timing closure, and post-silicon validation. As part of the team, you will be responsible for various key tasks including scan architecture planning, pin mixing, scan compression planning, and optimization for pattern volume for SA and TD pattern sets. Your expertise will be crucial in scan synthesis, power optimization techniques in test modes, MBIST architecture planning, repair architectures, insertion, verification, and analog and mixed signal IP testing architecture and verification. In this role, you will also be involved in timing closure of scan, MBIST, and other test modes, writing SDCs, understanding timing exceptions, debugging timing issues with the PD team, performing timing GLS, and debugging fails in simulations. Post-silicon validation, interpretation of tester results, debugging IR drop issues, and diagnostics of silicon failures will also be within your scope of responsibilities. Understanding of JTAG operation and debug is required, with knowledge of iJTAG protocol being desirable. Additionally, you will need to understand functional test cases, IO testing, and testing of ARM processor cores. As a Senior DFT Engineer, you must demonstrate the ability to lead a team across all aspects of DFT, interact effectively with RTL and physical design teams for DFT implementation, anticipate risks, plan project timelines, and milestones. The role requires a Bachelor's or Master's degree in Engineering with 5+ years of relevant experience. Samsung Semiconductor India Research (SSIR) values diversity and is committed to providing Equal Employment Opportunity to all individuals, irrespective of their religion, gender, age, marital status, gender identity, veteran status, genetic information, disability status, or any other characteristic protected by law.,

Posted 6 days ago

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