DFT Design Engineer - Foundry Team

The position available involves working with Samsung Semiconductor India Research (SSIR), an innovative hub focused on developing cutting-edge semiconductor solutions. As part of one of the largest R&D centers for Samsung Electronics outside Korea, you will have the opportunity to work on advanced technologies in System LSI, Memory, Foundry, and more. Your role will entail collaborating on diverse projects, conducting research in emerging technology areas, and contributing to the development of world-class products. We are seeking a professional with over 5 years of experience in full chip Design for Testability (DFT) architecture, implementation, timing closure, and post-silicon validation. Your expertise should cover areas such as scan architecture planning, MBIST architecture, analog and mixed-signal IP testing, and timing closure for various test modes. You should be adept at leading a team, coordinating with RTL and physical design teams, and managing project timelines effectively. The ideal candidate will hold a B.Tech/B.E/M.Tech/M.E degree with a strong background in DFT methodologies. Knowledge of JTAG operation, iJTAG protocol, and functional testing is essential for this role. Additionally, you should have a proactive approach to identifying risks, troubleshooting timing issues, and ensuring high reliability and performance in semiconductor testing. Samsung Semiconductor India Research (SSIR) is committed to fostering a diverse and inclusive work environment, offering Equal Employment Opportunity to all individuals. Regardless of your background, SSIR values creativity, innovation, and a collaborative spirit in driving technological advancements. If you meet the qualifications and are excited about working on cutting-edge technologies with a global leader in semiconductor solutions, we encourage you to apply for this challenging and rewarding opportunity.,