Design For Test Engineer (DFT) Silcosys Solutions

8.0 - 13.0 years

4 - 8 Lacs

Noida, Hyderabad, Bengaluru

Work from Office

We are seeking a highly experienced Senior DFT Engineer with 8+ years of hands-on expertise in developing and implementing DFT architectures for complex SoCs. The ideal candidate should have a solid background in scan insertion, ATPG, BIST, and silicon debug. Key Responsibilities: Define and implement DFT architecture for digital and mixed-signal SoCs Perform scan insertion, boundary scan, and ATPG pattern generation Integrate Memory BIST (MBIST) and Logic BIST (LBIST) Drive DFT verification and post-silicon validation/debug Collaborate with RTL, synthesis, STA, and backend teams to ensure testability Ensure high test coverage, test time optimization, and compliance with ATE requirements Requirements: 8+ years of experience in DFT implementation and verification Hands-on experience with tools like Tetramax, TestMax, Fastscan, or MBISTArchitect Strong understanding of scan/ATPG, JTAG, BIST, and IEEE 1149.x standards Experience in silicon bring-up, failure analysis, and debug Familiarity with industry-standard flows and ATE constraints Excellent problem-solving and team collaboration skills How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of DFT.

Posted 1 week ago

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