4.0 - 10.0 years

0 Lacs

karnataka

On-site

The role requires you to execute small to mid-size customer projects in various fields of VLSI Frontend, Backend, or Analog design with minimal supervision. As an individual contributor, you will be responsible for owning specific tasks related to RTL Design/Module and providing support to junior engineers in areas such as Verification, PD, DFT, Circuit Design, Analog Layout, STA, Synthesis, Design Checks, and Signoff. It is crucial to independently analyze and complete assigned tasks within the defined domain successfully and on-time, ensuring on-time quality delivery approved by the project lead/manager. You will be evaluated based on the quality of deliverables, timely delivery, reduction in cycle time and cost using innovative approaches, number of trainings attended, and number of new projects handled. Your responsibilities will include ensuring clean delivery of designs and modules, meeting functional specifications and design guidelines without deviation, and documenting tasks and work performed. Additionally, you must meet project timelines, support the team lead in intermediate task delivery, actively participate in team work, and perform additional tasks if required. In terms of innovation and creativity, you are expected to automate repeated tasks to save design cycle time, actively participate in technical discussions, and engage in training forums. Your skills should include proficiency in languages such as System Verilog, Verilog, VHDL, UVM, C, C++, Assembly, Perl, TCL/TK, and Makefile. Familiarity with EDA Tools like Cadence, Synopsys, Mentor tool sets, and various simulators is essential. Technical knowledge in areas like IP Spec Architecture Design, Micro Architecture, Bus Protocols, Physical Design, Circuit Design, Analog Layout, Synthesis, DFT, and technology nodes like CMOS FinFet is required. Strong communication skills, analytical reasoning, problem-solving abilities, attention to detail, and the capability to deliver tasks on-time while maintaining quality guidelines are crucial for this role. You should possess the necessary technical skills and prior design knowledge to execute assigned tasks and demonstrate the ability to learn new skills if required. Additionally, you should have project experience in RTL Design, Verification, DFT, Physical Design, STA, PV, Circuit Design, or Analog Layout, and a strong understanding of design flow and methodologies used in designing. As part of a global digital transformation solutions provider like UST, you will have the opportunity to work on cutting-edge technologies and projects with GHz frequency range. You will be responsible for tasks related to Physical Design, Timing Closure, Synthesis, Timing Analysis (STA), CTS, and other relevant activities for complex multi-clock, multi-voltage SoCs. Desired skills for this role include expertise in synthesis of complex SoCs, writing timing constraints for complex designs, post-layout timing analysis, I/O constraints development for industry standard protocols, knowledge of EDA tools, VLSI process, device characteristics, and deep submicron effects. Join UST, a company that is committed to digital transformation and innovation, working alongside the world's best companies to make a real impact through transformation. With deep domain expertise, a future-proof philosophy, and a global presence, UST offers opportunities to embed innovation and agility into client organizations, touching billions of lives in the process.,

Posted 2 days ago

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Analog Layout Engineer Acesoft Labs

3.0 - 8.0 years

3 - 8 Lacs

Hyderabad

Work from Office

Responsible for Design and development of critical analog, mixed-signal, custom digital block, and full chip level integration support. • Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must. • Perform layout verification like LVS/DRC/Antenna, quality check and support documentation. • Responsible for on-time delivery of block-level layouts with acceptable quality. • Excellent problem-solving skills in physical verification of custom layout. • Demonstrate high quality and accurate execution to meet project schedule/milestones in multiple project environment. • Ability to guide junior team-members in their execution of Sub block-level layouts & review critical items. • Contribute to effective project-management. • Effectively communicating with Local engineering teams to assure the success of layout project. Educational Background • BE or MTech in Electronic/VLSI Engineering • 3 + year experience in analog/custom layout design in advanced CMOS process. NOTE: **custom layout or analog layout with TSMC 3nm/5nm7nm & 5+ exp ****

Posted 1 week ago

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