2 - 8 years
4 - 10 Lacs
Posted:2 weeks ago|
Platform:
Work from Office
Full Time
B.E. in Electronic & Communication Engineering or related field with a minimum of 60% aggregate 2 to 8 years of experience in VHDL coding for both RTL and test bench Proficient in digital design using FPGAs, preferably Xilinx FPGAs Familiar with FPGA design and verification flow Good in using Xilinxs Vivado Familiar with Vivado simulators Familiar with debug tools like Xilinx ILA Knowledge of telecom/networking domain protocols is an added advantage Experience in timing analysis Experience in RTL design for high-speed design Good communication skills Responsibilities : Develop and test FPGA designs for a variety of applications, including Ethernet MAC, Ethernet PHY, GMII, RGMII, AXI4-Stream, MDIO, I2C, DDR2/DDR3/DDR4, PCIe, SPI, FIFOs, and BRAM Write VHDL code for both RTL and test bench Work with digital design using FPGAs, preferably Xilinx FPGAs Follow the FPGA design and verification flow Use Xilinx's Vivado and Vivado simulators for design and simulation Use debug tools like Xilinx ILA Analyze timing for high-speed designs Collaborate with other engineers and team members to ensure the successful completion of projects Keep up-to-date with new technologies and techniques in the field of FPGA design
GL Communications India
Upload Resume
Drag or click to upload
Your data is secure with us, protected by advanced encryption.
Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.
We have sent an OTP to your contact. Please enter it below to verify.
Instantly access job listings, apply easily, and track applications.
4.0 - 10.0 Lacs P.A.
Vadodara
9.0 - 16.0 Lacs P.A.
Aurangabad, MIDC Chikalthana
4.0 - 6.0 Lacs P.A.
3.5 - 5.0 Lacs P.A.
Hyderabad
7.0 - 11.0 Lacs P.A.
Bengaluru
5.0 - 9.0 Lacs P.A.
6.0 - 10.0 Lacs P.A.
Bengaluru
6.0 - 10.0 Lacs P.A.
4.0 - 7.0 Lacs P.A.
6.0 - 8.0 Lacs P.A.
