DV Engineer

PFB the JD.

JD Lead: 1 or 2 or 3 based on the options we get

• 15+ years of experience in Design Verification
• Strong experience in Processor based SoC verification
• Strong experience in ARM Cortex M or A series designs. Must have worked on bringing up the boot code, writing ISR, exceptions and other functions
• Strong experience in System Verilog and UVM based design verification
• Experience in Tensilica xtensa designs is a big plus
• Must have lead at least 2 to 3 SoC DV or Processor subsystem projects with a team size of 10+ Engineers
• Must have strong experience in AMBA protocols
• Must have strong understanding of functioning of Cache controllers, DMA & memory management controllers/ techniques

JD Engineer: 9 members

1. 3 to 10 years of experience in Design Verification

2. Good experience in Processor based SoC Verification is a must

3. Experience in writing C or Assembly testcases is a must

4. Strong experience in AHB or AXI protocol is a must

5. System Verilog and UVM experience is a must

JD Engineer: 6 members

1. 3 to 10 years of experience in Design Verification

2. Good experience in Processor based SoC Verification is a must OR strong experience in IP verification using SV/ UVM is a must

3. Experience in writing C or Assembly testcases is a plus

4. Strong experience in AHB or AXI protocol is a must

Location:

1. Pune or Noida or Bangalore

2. Each location needs a lead + team of 3 to 4 to a minimum

3. If we can set it up in one location that would be great