Design and Verification Engineer

Design Verification Engineer (5-7 years experience)

Company:

Job Summary:

We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools.

Responsibilities:

• Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM)
• Design and write robust verification environments (testbenches) to achieve high code coverage
• Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality
• Debug and analyze verification failures to identify the root cause of design issues
• Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements
• Participate in code reviews and ensure adherence to verification coding standards
• Stay up-to-date with the latest verification tools and methodologies

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
• 5-7 years of experience in design verification for ASICs or SoCs
• Strong understanding of digital design principles (combinational logic, sequential logic)
• Proven ability to develop and debug complex verification environments
• Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM)
• Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus
• Excellent analytical and problem-solving skills
• Strong communication and collaboration skills to work effectively in a team environment

Benefits:

• Competitive salary and benefits package
• Opportunity to work on leading-edge technologies and projects
• Collaborative and dynamic work environment
• Potential for professional development and career advancement

Design Verification Engineer (7-10 years experience)

Company:

Job Summary:

We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits.

Responsibilities:

• Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification)
• Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage
• Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality
• Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues
• Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence
• Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment
• Participate in code reviews and champion best practices for verification code quality
• Stay current with the latest advancements in verification tools and methodologies

Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus)
• 7-10 years of solid experience in Design Verification for ASICs or SoCs
• In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
• Proven ability to develop, debug, and optimize complex verification environments
• Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)
• Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)
• Experience with formal verification tools and techniques is a plus
• Excellent analytical and problem-solving skills with a meticulous attention to detail
• Strong communication, collaboration, and leadership skills to effectively contribute and guide the team

Benefits:

• Competitive salary and benefits package commensurate with experience
• Opportunity to work on leading-edge technologies and projects with a high impact
• Collaborative and dynamic work environment that fosters continuous learning
• Potential for professional development and career advancement