21 Clp Jobs

Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/SystemVerilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment.

Job Description: We are looking for a RTL Design Engineer with expertise in SoC and IP-level design and integration. The ideal candidate should have a strong background in RTL coding, architecture-level understanding, and industry-standard quality checks and tools. Key Responsibilities: Develop RTL code in Verilog/SystemVerilog Understand and apply top-level SoC architecture concepts Perform SoC and IP-level integration Implement RTL quality checks including CLP (mandatory), LINT, CDC, RDC, VSI Work on design partitioning (Tilification) Handle IORING, PHYs, GPIOs Collaborate with verification and backend teams Required Skills: RTL coding in Verilog and SystemVerilog IPXACT knowledge Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) UPF and SDC concepts Tools: VC_static, SpyGlass (Lint, CDC, RDC), 0in, Formality, Conformal LEC Scripting: Perl, Python, TCL Nice to Have: Experience with design quality metrics and standards Exposure to physical-aware RTL design

Immediate Openings on SYNON 2E RPG AS400_Pan India_Contract Experience 7+ Years Skills Oracle Apps Techno Functional Location Chandigarh,Dadra & Nagar Haveli , Daman , Diu , Goa , Haveli , Hyderabad , Jammu , Lakshadweep , Nagar , New Delhi,Puducherry,Sikkim, Pan India Notice Period Immediate . Employment Type Contract SYNON 2E, RPG AS 400 1. CL programming 2. RPGLE and RPG programming 3. Screen Design Aid Subfiles 4. Printer Files 5. AS/400 Query skills 6. AS400 Database Skills - creating files understanding relationship between logical & physical files 7. Experience of ERP systems 8. Legacy interfacing with other systems

Develop and maintain applications using RPG ILE, RPGLE, and CLLE programming languages on the AS400 platform. You will work with DB2 databases, write queries, and ensure system optimization. Expertise in AS400 systems, RPG programming, and DB2 is essential for this role.

Develop, maintain, and troubleshoot AS/400 applications using Control Language Programming (CLP) to ensure optimal system performance. This role requires experience in RPG, CLP, and AS/400 system administration for efficient application support and maintenance.

Write clean, well-engineered code that is readable, adequately commented, robust, and adheres to standards.Develop and test programming modifications.Integrate software with existing systems.Analyze performance of programs and take action to correct deficiencies based on consultation with Client and approval of Technical Lead.Create and maintain programming documentation.Adaptability for different Technologies.Added Advantage for having experience in Banking/Financial Domain Excellent knowledge and experience in AS400 System.Good Knowledge in DB2/400, SQL.Efficient Programming in CLP / ILE concepts / SQLRPGLE

RPG Developer Basic knowledge of DB2 400 database. Experience of working on Healthcare Provider and Payer applications Advanced knowledge of RPGLE concepts as well as practical programming knowhow Working knowledge of the CL environment. A sound understanding of the basics of ILE Advanced Concepts especially the Service Programs/Binding gdirectory, etc. Well versed Batch Job handling, debugging and Job servicing. A good knowledge of Job scheduling. Knowledge of Job schedulers/RBO schedulers A basic knowledge of the concept of FTP methodology and its working An expert understanding of running queries and fetching relevant SQL results. A basic understanding of Triggers/Stored procedures. - Knowledge of Java would be looked forward to A sound understanding of the HAWKEYE tool would be a great advantage . Hands on experience of ServiceNow, JIRA, ITSM/ITIL Process framework, workflows and methodologies in application support environment. Work Timings2:30 PM to 12:30 am IST.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm's Bangalore WLAN PHY (Baseband) team is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. Our WLAN PHY team, comprised of highly passionate and seasoned domain experts, prides itself on years of experience in taking WLAN PHY designs from concept to silicon independently. WLAN PHY team is responsible for delivering the end-to-end Tx/Rx DSP chains – all the way from antenna samples post ADC to raw bits for upper layers and on the reverse path from raw bits to DAC. The team specializes in working with challenges of practical high-speed wireless communication systems and finding innovative solutions to counter them. The team works extensively on typical signal processing functions like filters, matrix transformations (e.g.QR, Cholesky decomposition), channel estimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, and contributes to the development/ enhancement/ evaluation of signal processing algorithms to cater to new requirements. We are looking for someone as passionate as us and takes pride in their work. WiFi's ubiquity in modern times is undeniable, and the IEEE 802.11 Working Group is continually developing new standards to satisfy the growing demand for high throughput and low-latency real-time applications, such as VR and AR. Qualcomm is at the forefront of the WiFi revolution, aiming to become the global leader in WiFi chip solutions. The WLAN PHY team in Bangalore is instrumental in realizing this vision. : Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs. Expertise in digital design, VLSI concepts, and experience in creating power/area-efficient IPs across multiple clock domains are essential. Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected. Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review. Experience in leading, guiding, or managing junior team members is advantageous. Repeated success in taking IP designs from requirements to silicon is required. While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial. Skills: Must have: Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication, analytical & leadership skills. Good to have: System Verilog, Visio, Knowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax), experience with HLS. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Optum is a global organization that delivers care, aided by technology to help millions of people live healthier lives. The work you do with our team will directly improve health outcomes by connecting people with the care, pharmacy benefits, data and resources they need to feel their best. Here, you will find a culture guided by inclusion, talented peers, comprehensive benefits and career development opportunities. Come make an impact on the communities we serve as you help us advance health optimization on a global scale. Join us to start Caring. Connecting. Growing together. Primary Responsibilities: Be able to lead the deliveries end to end Prepare detail design documents based on HLD. Consult with System Analyst, Subject Master Expert, users to evaluate business requirements, evaluate existing or proposed systems, and prepare detailed technical design document from which programs will be written Walk-thru the technical design document with SA/SME/QA group and support team Review the details design & develop or modify the existing batch or online modules programs Ensuring timely deliveries for all assigned tasks Participation in Design reviews, Test Case reviews, and Production Support readiness reviews for new releases Support QA, UAT and Release phases of the project via defect analysis, change maintenance, etc.Adhere to all quality requirements Be able to work independently Comply with the terms and conditions of the employment contract, company policies and procedures, and any and all directives (such as, but not limited to, transfer and/or re-assignment to different work locations, change in teams and/or work shifts, policies in regards to flexibility of work benefits and/or work environment, alternative work arrangements, and other decisions that may arise due to the changing business environment). The Company may adopt, vary or rescind these policies and directives in its absolute discretion and without any limitation (implied or otherwise) on its ability to do so #NJB #NIC Required Qualifications: Undergraduate degree or equivalent experience 5+ years of IT experience on AS400 technologies Experience in RxClaim core adjudication area Hands-on experience in DB2/400 Experience to participate in Design reviews, Test Case reviews, and Production Support readiness reviews for new releases Experience to support QA, UAT and Release phases of the project via defect analysis, change maintenance, etc. Solid knowledge and hands on experience on SYNON Solid knowledge on SQL Demonstrated ability to ensure timely deliveries for all assigned tasks Demonstrated ability to adhere to all quality requirements Demonstrated ability to work independently. Proven good communication and presentation skills Proven good attitude and self-motivated Proven adaptable to work in Evening shift (11:30 am 8.30 pm or 2:30 pm 12:00 am) At UnitedHealth Group, our mission is to help people live healthier lives and make the health system work better for everyone. We believe everyoneof every race, gender, sexuality, age, location and incomedeserves the opportunity to live their healthiest life. Today, however, there are still far too many barriers to good health which are disproportionately experienced by people of color, historically marginalized groups and those with lower incomes. We are committed to mitigating our impact on the environment and enabling and delivering equitable care that addresses health disparities and improves health outcomes an enterprise priority reflected in our mission.

Project Role : Full Stack Engineer Project Role Description : Responsible for developing and/or engineering the end-to-end features of a system, from user experience to backend code. Use development skills to deliver innovative solutions that help our clients improve the services they provide. Leverage new technologies that can be applied to solve challenging business problems with a cloud first and agile mindset. Must have skills : Python (Programming Language), RPGLE, CLP Good to have skills : NAMinimum 7.5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Full Stack Engineer, you will be responsible for developing and engineering the end-to-end features of a system, from user experience to backend code. Your typical day will involve collaborating with cross-functional teams to design and implement innovative solutions that enhance client services. You will leverage new technologies and methodologies to address complex business challenges, all while maintaining a cloud-first and agile mindset. Engaging in problem-solving and continuous improvement will be key aspects of your role, ensuring that the systems you develop are efficient, scalable, and user-friendly. Roles & Responsibilities:- Expected to be an SME.- Collaborate and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Mentor junior team members to enhance their skills and knowledge.- Continuously evaluate and improve development processes to increase efficiency. Professional & Technical Skills: - Must To Have Skills: Proficiency in Python (Programming Language).- Strong understanding of web development frameworks such as Django or Flask.- Experience with front-end technologies including HTML, CSS, and JavaScript.- Familiarity with database management systems like PostgreSQL or MySQL.- Knowledge of cloud services and deployment strategies. Additional Information:- The candidate should have minimum 7.5 years of experience in Python (Programming Language).- This position is based at our Pune office.- A 15 years full time education is required. Qualification 15 years full time education

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm's Bangalore WLAN PHY (Baseband) team is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards. Our WLAN PHY team, comprised of highly passionate and seasoned domain experts, prides itself on years of experience in taking WLAN PHY designs from concept to silicon independently. WLAN PHY team is responsible for delivering the end-to-end Tx/Rx DSP chains- all the way from antenna samples post ADC to raw bits for upper layers and on the reverse path from raw bits to DAC. The team specializes in working with challenges of practical high-speed wireless communication systems and finding innovative solutions to counter them. The team works extensively on typical signal processing functions like filters, matrix transformations (e.g.QR, Cholesky decomposition), channel estimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, and contributes to the development/ enhancement/ evaluation of signal processing algorithms to cater to new requirements. We are looking for someone as passionate as us and takes pride in their work. WiFi's ubiquity in modern times is undeniable, and the IEEE 802.11 Working Group is continually developing new standards to satisfy the growing demand for high throughput and low-latency real-time applications, such as VR and AR. Qualcomm is at the forefront of the WiFi revolution, aiming to become the global leader in WiFi chip solutions. The WLAN PHY team in Bangalore is instrumental in realizing this vision. : Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs. Expertise in digital design, VLSI concepts, and experience in creating power/area-efficient IPs across multiple clock domains are essential. Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected. Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review. Experience in leading, guiding, or managing junior team members is advantageous. Repeated success in taking IP designs from requirements to silicon is required. While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial. Skills: Must have: Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication, analytical & leadership skills. Good to have: System Verilog, Visio, Knowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax), experience with HLS. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Summary We are seeking a highly skilled Technical Lead with 6 to 10 years of experience in AS/400 Utilities CLLE RPGLE DB2/400 CLP and AS/400 RPG. The ideal candidate will work in a hybrid model during day shifts and will not be required to travel. This role involves leading technical projects ensuring high-quality deliverables and contributing to the companys success. Responsibilities Lead the development and maintenance of applications using AS/400 Utilities CLLE RPGLE DB2/400 CLP and AS/400 RPG. Oversee the design coding testing and implementation of software solutions to meet business requirements. Provide technical guidance and mentorship to junior developers and team members. Collaborate with cross-functional teams to gather and analyze requirements for new projects. Ensure that all software solutions are developed in compliance with industry standards and best practices. Troubleshoot and resolve technical issues in a timely manner to minimize downtime and ensure smooth operations. Conduct code reviews to ensure code quality performance and security. Develop and maintain technical documentation for all projects and processes. Participate in project planning and provide accurate estimates for development tasks. Monitor and optimize system performance to ensure efficient use of resources. Stay updated with the latest technologies and trends in AS/400 and related fields. Communicate effectively with stakeholders to provide project updates and address any concerns. Contribute to the continuous improvement of development processes and methodologies. Qualifications Possess strong experience in AS/400 Utilities CLLE RPGLE DB2/400 CLP and AS/400 RPG. Demonstrate excellent problem-solving skills and the ability to troubleshoot complex technical issues. Exhibit strong communication and interpersonal skills to work effectively with team members and stakeholders. Show proficiency in project planning and task estimation. Have a keen eye for detail and a commitment to delivering high-quality software solutions. Display the ability to work independently and as part of a team in a hybrid work model. Maintain a proactive approach to learning and staying current with industry trends and technologies.

In this role, you will work closely with layout, DRC/LVS, and tapeout teams to perform physical signoff checks, including Design Rule Checks (DRC), Layout Versus Schematic (LVS), and Electrical Rule Checks (ERC) using industry-standard EDA tools

SUMMARY Job Role: AS400 With COBOL Professionals Location: Hyderabad Experience: The ideal candidate should possess at least 2 years of relevant experience in AS400 with COBOL development. Requirements Skilled in AS400 (Cobol) technology with good technical and analytical skills. Knowledge of the Banking domain. Good communication skills. Additional Experience Experienced in AS400 in COBOL, not in AS400 in RPG/RPGLE. Experienced in COBOL for AS400, not for COBOL in the Mainframe. Experienced in AS400, not in ASIA LIFE, SMART/400, and other similar tools. CE and CLLE DB2 / 400 Tools - SEU, DFU, SDA Interactive or batch programming Subfiles Hawkeye DBU SQL / 400, Query / 400 OS / 400 Modularization, writing batch process, etc. Knowledge on Change management tools like Turnover, Implementer, and Aldon. Good understanding of ILE Concepts, Activation Groups, Service Programs, Binding Directory At least 2 years of relevant experience in AS400 with COBOL development. Knowledge of Banking domain. Good communication skills.

Job Summary The Engineering Manager will oversee the development and maintenance of software applications using AS/400 RPG COBOL/400 DB2/400 and CLP within the Cards & Payments domain. This role requires a strategic thinker who can manage hybrid teams ensuring projects are delivered on time and meet quality standards. The candidate will play a crucial role in enhancing the companys technological capabilities and driving innovation in the financial sector. Responsibilities Oversee the development and implementation of software solutions using AS/400 RPG COBOL/400 DB2/400 and CLP to meet business requirements in the Cards & Payments domain. Collaborate with cross-functional teams to ensure seamless integration of new technologies and processes. Provide technical guidance and support to team members fostering a collaborative and innovative work environment. Ensure all projects adhere to industry standards and regulatory requirements maintaining the highest level of quality and security. Manage project timelines and resources effectively to ensure timely delivery of solutions. Evaluate and recommend new technologies and tools to enhance productivity and efficiency within the team. Monitor and report on project progress identifying and mitigating risks to ensure successful outcomes. Facilitate communication between stakeholders to ensure alignment on project goals and deliverables. Develop and implement strategies to optimize software performance and scalability. Drive continuous improvement initiatives to enhance the teams capabilities and overall project outcomes. Support the hybrid work model by coordinating remote and on-site activities to maximize team productivity. Utilize domain expertise in Cards & Payments to provide insights and recommendations for process improvements. Ensure the teams adherence to best practices in software development and project management. Qualifications Possess strong technical expertise in AS/400 RPG COBOL/400 DB2/400 and CLP essential for developing robust software solutions. Demonstrate extensive experience in the Cards & Payments domain providing valuable insights into industry trends and challenges. Exhibit excellent problem-solving skills and the ability to make informed decisions under pressure. Show proficiency in managing hybrid teams ensuring effective collaboration and communication. Have a proven track record of delivering projects on time and within budget showcasing strong project management skills. Display strong interpersonal skills capable of fostering a positive team environment and building relationships with stakeholders. Demonstrate a commitment to continuous learning and staying updated with the latest industry developments.

Roles and Responsibilities: 2 to 4 years experience in Development and Maintenance project with Strong background of working on AS400 / iSeries including experience in working on languages including RPG IV, RPG ILE, RPG Free, CL 400 (CLP), SQL. Skilled in Batch and Interactive programming. Skilled and experience working in projects using agile methodologies as a plus. Specific knowledge about INSURE as a plus. Specific knowledge about Insurance world as a plus.

Compute, UCS Manager Administration RBAC - Delegate and control user accessprivileges according to the role Communication Service- Configure CIM XML,HTTP, HTTPS, SMASH CLP, SNMP, SSH, and Telnet to interface Organizations -policies, pools, and service profiles CIMC - Close the KVM, vMedia, and SOLsessions Backup and Restore - full state, all configuration, systemconfiguration, and logical configuration backup Virtualization (VMware, 5.Xand 6.X) Installing and Managing, Administration, performance fine tune (host,VM, virtual Appliance, vCenter) Virtual Network Configuration Administration Virtual Storageconfiguration Administration Backup recovery Wintel Administration Investigate, debug and solve windows Operating System Analyze and update theplatforms where needed to keep them secure and compliant with any relevantsecurity standards Wintel Administration. Compute, UCS Manager Administration RBAC - Delegate and control user access privileges according to the role Communication Service- Configure CIM XML, HTTP, HTTPS, SMASH CLP, SNMP, SSH, and Telnet to interface Organizations - policies, pools, and service profiles CIMC - Close the KVM, vMedia, and SOL sessions Backup and Restore - full state, all configuration, system configuration, and logical configuration backup. Virtualization (VMware, 5.X and 6.X) Installing and Managing, Administration, performance fine tune (host, VM, virtual Appliance, vCenter) Virtual Network Configuration Administration Virtual Storage configuration Administration Backup recovery Wintel Administration Investigate, debug and solve windows Operating System Analyze and update the platforms where needed to keep them secure and compliant with any relevant security standards

You have an entrepreneurial spirit. You enjoy working as a part of well-knit teams. You value the team over the individual. You welcome diversity at work and within the greater community. You aren't afraid to take risks. You appreciate a growth path with your leadership team that journeys how you can grow inside and outside of the organization. You thrive upon continuing education programs that your company sponsors to strengthen your skills and for you to become a thought leader ahead of the industry curve. You are excited about creating change because your skills can help the greater good of every customer, industry and community. We are hiring a talented RPG EDI Description Bachelor's degree in Computer Science, Information Technology, or a related field. Proven experience as an RPG Developer/SME with a focus on EDI solutions in an AS/400 environment. Strong proficiency in RPG IV/ILE programming. In-depth knowledge of EDI standards (e.g., X12) and protocols (e.g., FTP, AS2). EDI X12 transaction sets like 850, 810, 856, 855, 997, 204, 214 etc. Experience with AS/400 system operations, including CL programming and DB2/400 database management. Excellent problem-solving skills and attention to detail. Strong communication and interpersonal skills to work effectively with cross-functional teams and external partners. Ability to work independently and manage multiple tasks simultaneously. As far as RPG skills, our programs are written in RPG III, RPG400, and RPGLE, with a little RPG Free. We also have CL programs, so we would want someone very familiar with structured CL programming skills. The expectation is that they can proficiently read, analyze, debug, and code the various versions of RPG and CL code.

Job Information Job Opening ID ZR_1676_JOB Date Opened 21/12/2022 Industry Technology Job Type Work Experience 2-4 years Job Title AS400 Developer City Chennai Province Tamil Nadu Country India Postal Code 600001 Number of Positions 4 Roles and Responsibilities: 2 to 4 years experience in Development and Maintenance project with Strong background of working on AS400 / iSeries including experience in working on languages including RPG IV, RPG ILE, RPG Free, CL 400 (CLP), SQL. Skilled in Batch and Interactive programming. Skilled and experience working in projects using agile methodologies as a plus. Specific knowledge about INSURE as a plus. Specific knowledge about Insurance world as a plus. check(event) ; career-website-detail-template-2 => apply(record.id,meta)" mousedown="lyte-button => check(event)" final-style="background-color:#2B39C2;border-color:#2B39C2;color:white;" final-class="lyte-button lyteBackgroundColorBtn lyteSuccess" lyte-rendered=""> I'm interested

Dear Candidate, We are hiring a Prolog Developer to work on logic programming projects involving rule-based systems, AI inference engines, and natural language processing. Key Responsibilities: Design inference engines using Prolog or SWI-Prolog Build knowledge bases and implement predicate logic Integrate Prolog logic into modern applications via APIs or FFI Debug and optimize recursive query performance Collaborate on AI/NLP or knowledge graph projects Required Skills & Qualifications: Experience with Prolog , Horn clauses , and backtracking Familiarity with SWI-Prolog , Constraint Logic Programming (CLP) Background in AI , linguistics , or rule engines Bonus: Interfacing Prolog with Python , Java , or C Note: If interested, please share your updated resume and preferred time for a discussion. If shortlisted, our HR team will contact you. Kandi Srinivasa Reddy Delivery Manager Integra Technologies

Role & responsibilities Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/System Verilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment. Preferred Skills : Experience with complex subsystems such as memory controllers, interconnects, or high-speed I/O. Prior experience working with large, cross-functional teams and managing design schedules. Experience with software tools for RTL analysis and optimization. Hands-on experience in leading ASIC projects from specification to production.