Analog Mixed-Signal (AMS) Engineers

Job Description

Lead/Senior Analog Mixed-Signal (AMS) Engineers Layout / Verification / Design Locations: Noida | Bangalore | Hyderabad Experience: 7-12 Years Domain: Semiconductor | Analog Mixed-Signal | Custom IP & SoC Design Role Overview: We are hiring skilled and experienced professionals across AMS Layout , AMS Design , and AMS Verification disciplines to join our high-performance analog design team. You will contribute to the development of high-precision, low-power analog and mixed-signal IPs and subsystems targeted at next-generation SoCs in automotive, networking, and consumer electronics domains. Open Positions: Position #1: AMS Layout Engineer Responsibilities: Perform custom layout design of analog and mixed-signal circuits (e.g., ADCs, PLLs, LDOs, Bandgap, Bias, SerDes). Ensure layout quality, LVS/DRC clean , and meet area/power/performance targets. Work closely with circuit designers for floorplanning and layout optimization. Experience in FinFET nodes (e.g., 7nm/5nm) is a strong plus. Tools & Skills: Cadence Virtuoso (Layout XL), Calibre (LVS/DRC), PVS, Assura Strong grasp of matching, isolation, shielding, and analog layout best practices Position #2: AMS Design Engineer Responsibilities: Design and implement key analog/mixed-signal blocks such as amplifiers, voltage regulators, PLLs, SERDES, data converters, and ESD protection. Drive top-down design , simulation, and verification from spec to tape-out. Perform circuit simulation, characterization, and corner analysis . Tools & Skills: Cadence Spectre, Eldo, HSPICE, MATLAB, ADE-XL Good understanding of noise, mismatch, stability, and PVT simulations Position #3: AMS Verification Engineer Responsibilities: Develop AMS simulation environments integrating digital RTL and analog behavioral models. Use mixed-signal verification methodologies to validate complex AMS SoC subsystems. Support behavioral modeling (Verilog-A/AMS) and co-simulation using tools like Xcelium or AMS Designer. Tools & Skills: Verilog-AMS, SystemVerilog, UVM-MS, Cadence AMS Designer, Spectre AMS, Xcelium Knowledge of DFT hooks in analog blocks , test modes, and power intent is a plus Interested? Apply or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com