8 Amba Protocols Jobs

15+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering

Role & responsibilities "You will be closely working with Architecture Team, SOC Design Team, Product Design, Software Teams; Understand the requirement, enhancements required etc; create a realistic schedule and resource plan You will completely own the IP Design; preparing the micro-architecture, detailed design document, implement design using RTL coding techniques, performing reviews and ensuring all quality criteria are met Work with verification team on reviewing the verification test plan to ensure design features are verified correctly, issue debug, coverage analysis etc Provide support to SOC Integration, Physical Design, Software, Product Engineering team on pre & post silicon activities on need basis" Preferred candidate profile - Min 7 years full time experience in IP design, Detailed understanding of SOC Design - Good understanding and Hands on experience in interconnect designs, multi-clock designs, SoC BUS architecture and NOC concept; - Experience in performance and latency tuning will be an add-on - Proficiency in IP Design using Verilog, System Verilog hardware logic design language - Sound knowledge of AMBA protocols like APB/AHB/AXI/ACE/ACE-Lite -Self-driven, Strong problem solving, root causing and debugging skill -Experience in creating documents such as micro-architecture, hardware design document, verification request etc -Work collaboratively with other members of the IP Team, SOC Team, cross-functional teams across various geographies - Good written and verbal communication skills

Understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design for some of the components of the Test Environment for the DesignWare family of synthesizable cores in protocol areas such as Ethernet/DSC/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/ USB/ MIPI Be an individual contributor in the Verification Tasks - Architect testbenches, coding of TE, debug, verification coverage improvement, etc. Will contribute to technical review of TE Code of medium complexity. Will contribute to technical process and quality improvement to achieve high quality deliveries Will be expected to Solve complex/ abstract problems The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in CRV environment. The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide. May need to take the role of technical lead for a few of the components of the Test Environment and achieve high quality verification with a small team of verification engineers. The role offers ample scope to mentor junior engineers and interns and to enhance ones leadership skills. Key Qualifications and Experience Must have BSEE/ MSEE in EE with 6 to 12 years of relevant experience in the following areas: Verification of IP Cores or SoC Designs for Set Top Boxes, Mobile handsets, Smart Devices, etc. Knowledge of one or more of protocols: Ethernet/AMBA (AMBA2, AXI, CHI)/ SD/eMMC/USB/ DDR/PCIe MIPI/DSC. Knowledge of Ethernet protocol will be plus. Hands on experience with creating detailed design of components of Test Environment from Functional Specifications/ Test Environment Specifications. The TE must have used methodologies such as UVM, OVM Test Planning, Coverage Planning, Assertion Planning Hands on experience with System Verilog coding and Simulation tools; Deep Knowledge of OOPs Concepts Experience with Perforce or similar revision control environment Knowledge of Perl/Shell scripts. Exposure to quality processes in the context of IP design and verification is an added advantage In addition, the candidate should have good communication skills, will be a team player, and will have good problem-solving skills.

Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience inVerilog/System-Verilogis a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime isrequired. Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements: 2+ years of experience with abachelors/masters degree in Electrical engineering

12+ years of experience in SoC design Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12+ years of experience with a Bachelors/ masters degree in Electrical/ Electronics engineering

Expertise in AMBA protocols (CHI/AXI/AHB) Excellent analytical skills, should have an experience of leading a team of 7-8 engineers Knowledge of ARM architecture be an added advantage Exposure to low power methodology with understanding of UPF Handson experience of GLS and timing simulations Exposure to Formal verification Self-driven and motivated to work in a high pressure environment Good at stakeholder management with good communication skills Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Qualcomm is not responsible for any fees related to unsolicitedresumes/applications.

Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration