5 Accelerators Jobs

As an experienced professional in ASIC development with a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, you will be leading a team of engineers in Bengaluru to deliver AI/ML compute intensive IPs and subsystems. With 8 years of experience in Verilog/SystemVerilog, VHDL, or Chisel, and 4 years of people management expertise, you will collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. Your responsibilities will include taking ownership of complex IPs or subsystems, implementing RTL, and driving design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Additionally, you will be tasked with identifying and driving power, performance, and area improvements for the domains owned. Your role will involve working on cutting-edge SoCs used to accelerate machine learning computation in data centers. You will be solving technical issues with innovative micro-architecture and practical logic solutions, and evaluating design options with complexity, performance, power, and area in mind. Furthermore, you will contribute to the innovation behind products loved by millions worldwide, leveraging your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The future of AI/ML hardware acceleration awaits you in this role, where you will have the opportunity to shape cutting-edge TPU technology that powers Google's most demanding AI/ML applications. You will be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. Your contributions will play a crucial role in delivering high-quality designs for next-generation data center accelerators, collaborating with various teams such as architecture, verification, power and performance, and physical design. The Technical Infrastructure team at Google is responsible for the architecture that keeps everything running smoothly online. From data centers to the next generation of Google platforms, this team ensures Google's product portfolio remains at the forefront of innovation. By joining this team, you will play a key role in maintaining networks, ensuring users have the best and fastest experience possible.,

The Product Owner (ISG) will play a crucial role in driving the success of Guidewire implementations, particularly focusing on Guidewire Ins Suite Integration and ClaimCenter to ensure seamless integration and functionality. You are expected to have a deep understanding of Guidewire tools and accelerators, and the ability to work effectively in a hybrid work model. Collaboration with cross-functional teams is essential to deliver high-quality solutions. As the Product Owner, your responsibilities include leading the development and implementation of Guidewire solutions in alignment with business objectives, overseeing the integration of Guidewire Ins Suite with a focus on ClaimCenter for enhanced operational efficiency, and collaborating with stakeholders to gather and prioritize requirements accurately reflected in the product backlog. You will provide guidance and support to development teams, monitor project progress, address issues for timely delivery, facilitate communication between technical and non-technical teams, evaluate and recommend Guidewire tools and accelerators, conduct regular reviews of product features, coordinate with QA teams for testing, drive continuous improvement initiatives, ensure compliance with industry standards, support change management efforts, and maintain up-to-date knowledge of Guidewire products and industry trends to inform decision-making. To qualify for this role, you should possess extensive experience in Guidewire Ins Suite Integration with a focus on ClaimCenter, demonstrate proficiency in using Guidewire tools and accelerators, exhibit strong analytical and problem-solving skills, have a proven track record of managing Guidewire projects in a hybrid work environment, show excellent communication and collaboration skills, and display a commitment to continuous learning and staying current with industry advancements.,

A career in our Advisory Acceleration Centre is the natural extension of PwC's leading-class global delivery capabilities. We provide premium, cost-effective, high-quality services that support process,

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. You should possess at least 5 years of experience in ASIC development with Verilog/SystemVerilog and VHDL. It is essential to have experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). Additionally, experience in micro-architecture and design of subsystems is required. Preferred qualifications: Ideally, you should have experience in SoC designs and integration flows. Proficiency in scripting languages such as Python or Perl would be beneficial. Knowledge of high performance and low power design techniques is preferred, along with an understanding of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies. About the job: As a member of our team, you will contribute to shaping the future of AI/ML hardware acceleration, focusing on cutting-edge TPU (Tensor Processing Unit) technology that drives Google's most demanding AI/ML applications. Your responsibilities will involve verifying complex digital designs, specifically related to TPU architecture and its integration within AI/ML-driven systems. You will work on ASICs used to enhance data center traffic, collaborating with various teams to deliver high-quality designs for next-generation data center accelerators. Innovation, problem-solving, and evaluation of design options will be key aspects of your role, with a focus on micro-architecture and logic solutions. The ML, Systems, & Cloud AI (MSCA) organization at Google is responsible for designing, implementing, and managing the hardware, software, machine learning, and systems infrastructure for all Google services and Google Cloud. Prioritizing security, efficiency, and reliability, the team works towards shaping the future of hyperscale computing, impacting users worldwide. Responsibilities: - Own microarchitecture and implementation of subsystems in the data center domain. - Collaborate with Architecture, Firmware, and Software teams to drive feature closure and develop microarchitecture specifications. - Perform Quality check flows like Lint, CDC, RDC, VCLP. - Drive design methodology, libraries, debug, and code review in coordination with other IPs Design Verification (DV) teams and physical design teams. - Identify and implement power, performance, and area improvements for the domains owned.,

You are Silicon Labs, a leader in secure, intelligent wireless technology for a more connected world. Your integrated hardware and software platform, intuitive development tools, unmatched ecosystem, and robust support make you the ideal long-term partner in building advanced industrial, commercial, home, and life applications. You make it easy for developers to solve complex wireless challenges throughout the product lifecycle and get to market quickly with innovative solutions that transform industries, grow economies, and improve lives. The Digital Architecture team at Silicon Labs is responsible for the research and development of digital architecture and IPs from concept to production. The team develops compute engines (AI/ML), processors (RISC-V), Audio and Video subsystems, accelerators, peripherals, bus fabric, internal communication systems, and system IP. The team focuses on IC architectures for multi-core, multithreaded SoCs with an energy-efficient compute backbone for IoT connectivity, security, and sensing subsystems. They engage in advanced research and development, high-level modeling, and architecture definition, valuing innovation, simplicity, quality, and smart development processes within a highly collaborative and learning-driven team. As a Staff Digital Architect at Silicon Labs, you will be responsible for designing and implementing robust digital architectures that support the business objectives of providing power-efficient, computation-intensive solutions for low-power embedded wireless devices. This role demands a deep understanding of digital technologies, strong analytical skills, and effective collaboration with cross-functional teams including IC and IP design, modeling, software, application, and marketing teams. Your responsibilities will include designing scalable and innovative digital architectures, leading technology evaluations and selections, collaborating with stakeholders to translate requirements into technical solutions, ensuring security, performance, and reliability of digital systems, providing technical leadership and mentorship, staying updated with industry trends, and documenting architectural solutions clearly. Required Experience & Skills: - Demonstrated experience in defining and designing high-complexity designs - Excellent understanding of embedded systems, hardware-software partitioning, performance, and power tradeoffs - Excellent verbal and written communications skills - Good understanding of low power design, HDL-based RTL logic design, front-end design tools, debug methodologies, and design for test and manufacturing Preferred Experience & Skills: - Experience in design of microprocessors, math-centric designs, and high-level software languages for modeling - Scripting skills in BASH, UNIX commands, Python, Perl, etc. Benefits & Perks: - Equity Rewards (RSUs) - Employee Stock Purchase Plan (ESPP) - Insurance plans with Outpatient cover - National Pension Scheme (NPS) - Flexible work policy - Childcare support Join Silicon Labs, where every engineer makes a significant impact on the product, and where you'll find a good work/life balance in a welcoming and fun environment.,