211 Ddr Jobs

BMC Firmware: Very strong in C language programming and debugging Working knowledge of git/gerrit Side-band/Out-of-band server management. Experience in Open BMC stack development mandatory. Memory Firmware Very strong in C language programming and debugging Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Power Management Firmware Very strong in C language programming and debugging Working knowledge of git/gerrit Good understanding and experience with BIOS, power management and PCIe Good knowledge SoC power management CPU/Device power states, hot-plug etc Strong knowledge of UEFI BIOS, ACPI. AGESA knowledge is a big plus Security Firmware Very strong in C language programming and debugging Working knowledge of git/gerrit Good knowledge about silicon security subsystem / policy, root of trust, TPM/fTPM, Widevine Good knowledge on security concepts like chain of trust , Crypto Algorithms. Good knowledge of trusted applications and handshake

Skills/Experience: Extensive experience in IP/SOC Verification. Must be proficient in System Verilog and UVM. Must have hands-on experience in the verification of the IP protocols such as PCIe/DDR/USB/Ethernet/CXL/HDMI/MIPI/DSI/CS/GLS/CPU Verification or any other high-speed protocols. Experience with scripting language (Python, Perl, TCL etc.) Experience in assembly language or C is a plus. Ability to create testbenches from scratch and own the complete verification including coverage of the subsystem/chip level. Strong debugging capabilities. Experience (years) : 3 - 12 Years Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer (B.Tech/ M.Tech) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. You've sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. You are a great teammate, resilient and sincere, Enjoy learning new things and build knowledge base in new area.

Responsibilities: *Strong knowledge of DDR protocols (DDR3/DDR4/LPDDR4/LPDDR5). *Proficiency in gate-level simulations and debugging. * Familiarity with JTAG-based testing and silicon validation flows. Contact: 7729881999 Office cab/shuttle Food allowance Health insurance Annual bonus Provident fund

Description: DDR and LPDDR design and analysis High speed serial IO design and analysis, PCIE, USB, UFS, CSI/DSI/MIPI Power Integrity analysis SI/PI tools :Ansys HFSS/SIwave, Cadence/Sigrity, Keysight ADS, HSPICE Spreadsheets and similar productivity tools Mentor or Cadence board design tools Requirements: The candidate is expected to perform SI / PI analyses and provide guidance on signal and power integrity challenges. Working effectively across organizational boundaries is essential as is the effective documentation and presentation of results. The candidate is expected to work closely with an experienced SI engineer while applying established PSIG methodologies. The engineer will have the opportunity to influence the evolution of analysis methodologies. Job Responsibilities: Perform various IO analyses using established methodologies, potentially from model extraction through simulation and reporting of conclusions. IO types include DDR memory interfaces and variety of serial interfaces. Analyze and provide design guidance for DIE floor plans, IC packages, PCB power distribution networks using established methodologies. Document, distribute, and present results at appropriate meetings. 4+ years of work experience in the following areas: Electromagnetic theory and transmission lines Basic signal and power integrity concepts Commercial 3D electromagnetic field solver Commercial SI or RF simulation and analysis tools SPICE transient simulation including use of IBIS models What We Offer: Exciting Projects: We focus on industries like High-Tech, communication, media, healthcare, retail and telecom. Our customer list is full of fantastic global brands and leaders who love what we build for them. Collaborative Environment: You Can expand your skills by collaborating with a diverse team of highly talented people in an open, laidback environment — or even abroad in one of our global centers or client facilities! Work-Life Balance: GlobalLogic prioritizes work-life balance, which is why we offer flexible work schedules, opportunities to work from home, and paid time off and holidays. Professional Development: Our dedicated Learning & Development team regularly organizes Communication skills training(GL Vantage, Toast Master),Stress Management program, professional certifications, and technical and soft skill trainings. Excellent Benefits: We provide our employees with competitive salaries, family medical insurance, Group Term Life Insurance, Group Personal Accident Insurance , NPS(National Pension Scheme ), Periodic health awareness program, extended maternity leave, annual performance bonuses, and referral bonuses. Fun Perks: We want you to love where you work, which is why we host sports events, cultural activities, offer food on subsidies rates, Corporate parties. Our vibrant offices also include dedicated GL Zones, rooftop decks and GL Club where you can drink coffee or tea with your colleagues over a game of table and offer discounts for popular stores and restaurants!

Skills/Experience: Independent layout development of High Speed blocks like SerDes, Rx, Tx, , PLL, ADC, LDO, Bandgap etc Strong debug skills and good communication Education Qualification: BE/B-Tech/ME/M-Tech degree in Electronics and Communication, Electrical Engineering, or related field.

Job Overview We are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams. Analyze and implement System Verilog assertions and coverage (code, toggle, functional). Provide mentorship and technical guidance to junior verification engineers.Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment. Ensure verification signoff criteria are met and documentation is comprehensive.Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines. Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies. Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence. Qualifications Bachelors degree in computer science, Electrical/Electronics Engineering, or related field. ORMasters degree in computer science, Electrical/Electronics Engineering, or related field. ORPhD in Computer Science, Electrical/Electronics Engineering, or related field. 5+ years of hands-on experience in SOC Design Verification. Expertise in UVM (Universal Verification Methodology) and System Verilog. Prior experience working on IP level and SOC level verification projects. Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs). Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols. Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF. Proficiency in scripting languages such as shell, Makefile, and Perl. Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment. C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.

Job Description We are looking for an experienced Design Verification Engineer to join our team and contribute to the verification of complex SoC/ASIC designs. The ideal candidate will have strong expertise in verification methodologies, testbench development, and debugging. Key Responsibilities: Develop and implement verification plans, environments, and testbenches using SystemVerilog/UVM. Write and execute test cases for functional, regression, and coverage-driven verification. Perform debugging and root cause analysis for design and verification issues. Collaborate with RTL design, architecture, and validation teams to ensure quality deliverables. Analyze functional coverage metrics and enhance test suites for improved quality. Work on assertion-based and formal verification techniques where applicable. Contribute to automation and scripting to streamline verification flows.

We are hiring Design Verification Engineers skilled in DDR, PCIe, and Ethernet . Must have strong System Verilog/UVM, protocol verification, debugging, and coverage closure expertise. Knowledge of AMBA, scripting, and simulation tools preferred. Provident fund

Job Roles: * Design DFT solutions using architecture, JTAG,VCS tools. * Strong knowledge of DDR protocols (DDR3/DDR4/LPDDR4/LPDDR5). * Proficiency in gate-level simulations Mail: chaitanya.vasamsetti@gigaopsglobal.com Contact: 7729881999 Office cab/shuttle Food allowance Health insurance Annual bonus Provident fund

You will play a crucial role in developing Interface and Analog IPs for internal ASIC or external customers. This will involve hands-on experience with Hard Analog or PHY blocks on circuit design using the latest finfet nodes like 16nm and 7nm. Your responsibilities will include driving processes to establish a solid IP Development methodology for successful outcomes with customers. Additionally, you should be able to provide support for multiple customers and IP Deliveries, possessing strong knowledge in all aspects of IP integration such as logic design and verification, physical design, packaging, test, and characterization. To excel in this role, you should have a minimum of 6 years of experience in IP Design and delivery of complex analog, mixed signal IPs or PHYs. Previous exposure to DDR, HBM, and SerDes is highly preferred. A Masters Degree or equivalent in Electronics and Computer Engineering is the minimum educational qualification required, with a preference for a PhD. Expertise in the complete ASIC and IP development life cycle is essential, along with a desire for hands-on engineering experience throughout the ASIC/IP development flow. Excellent verbal and written communication skills are crucial, including the ability to engage effectively with customers and vendors. As part of our commitment to employee well-being and satisfaction, we offer a comprehensive benefits package that includes competitive compensation, Restricted Stock Units (RSUs), opportunities for advanced education from Premium Institutes and eLearning content providers, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snacks facility. At Alphawave Semi, we prioritize Diversity & Inclusivity. We are an equal opportunity employer and encourage applications from all qualified individuals, including visible minorities, Indigenous People, and persons with disabilities. If you require accommodation as a qualified job applicant, we will work with you to provide reasonable accommodations tailored to your specific needs. If your application is selected to proceed in our hiring process, you will have the opportunity to request accommodations.,

You will be responsible for designing and developing FPGA and FPGA-based SoCs for new electronic products, ranging from simple hardware solutions to highly complex embedded processing systems. Your tasks will include developing detailed specifications based on requirements, implementing FPGA designs, collaborating with the design team to evaluate alternatives, performing implementation activities like timing analysis and simulations, preparing validation plans, and working on Xilinx Cores such as DDR4/LPDDR4/PCIE/USB/Ethernet IP cores. Additionally, you will debug using Chip scope/Protocol aware Logic Analyser/high-speed probes, collaborate with the verification team, participate in hardware bring-up, support hardware development through schematic design and PCB layout, and document ideas, designs, and specifications to Enercons standards. Mentoring junior members of the engineering staff will also be part of your responsibilities to promote design team abilities and establish good working practices. You should possess demonstrated skill in developing original designs with Verilog for FPGAs and/or FPGA-based SoCs, a strong understanding of FPGA design and architectural concepts, specific experience with common FPGA platforms such as Xilinx, and a working knowledge of tools and methodologies used in FPGA development. Experience with Xilinx family of SoCs and associated interfaces (AXI4 bus, High-speed transceivers, PCIe, DDR, etc.) is preferred. Additionally, you should have experience in hardware development including schematic and PCB layout tools, troubleshooting hardware issues using electronics lab equipment, and the ability to work with minimum supervision while following established design procedures. Good interpersonal skills and the ability to work between multiple departments are essential for this position. For this role, you are required to have a 4-year degree or equivalent experience in ECE Engineering or a related engineering discipline, along with a minimum of 5 years of FPGA development or equivalent experience. You should be able to demonstrate a sound understanding of the principles involved, possess a good academic background, and have the ability and enthusiasm to explore and work in new areas.,

You will be a key contributor to the design and development of high-speed, high-density printed circuit boards (PCBs) for embedded systems and IoT applications. You will work on designing Embedded Hardware Devices that will be used to integrate with the Building Automation units on the current architecture. This role involves working closely with cross-functional teams to deliver robust, manufacturable, and cost-effective PCB designs that meet performance and quality standards. Lead PCB Design Projects: Manage and execute PCB layout activities for rigid, flexible, and rigid-flex boards using advanced technologies (e.g., HDI, microvias, via-in-pad). Mentorship & Leadership: Mentor junior designers, conduct peer reviews, and ensure adherence to design best practices and standards. Tool Expertise: Utilize industry-standard tools Mentor Graphics Xpedition tool for schematic capture and PCB layout. Cross-functional Collaboration: Work closely with electrical, mechanical, and manufacturing engineers to resolve design issues and optimize for fabrication and assembly. Design Validation: Work closely with the manufacturing team to meet DFM/DFT and DFA checks. Perform impedance modeling, and thermal analysis to ensure robust and reliable designs. Documentation: Create and maintain design guidelines, templates, checklists, and project documentation. Process Improvement: Lead initiatives to evaluate and implement new design tools and methodologies. Supplier Interaction: Provide technical support to suppliers regarding PCB specifications and manufacturing queries. Work closely from Electrical and Mechanical aspects to create schematic symbols, PCB mechanical restriction guidelines, PCB component footprints and 3D component models. Responsible for completing PCB designs by agreed project time, cost, quality, and performance requirements. BE (ECE/EIE/EEE) - minimum 8+ years of experience in Mentor Graphics Xpedition tool. Knowledge of EMC/EMI design considerations. Very strong high-speed and multilayer layout skills including stack-up design, differential pair, impedance control, matched delay, etc. Strong understanding of signal integrity, power integrity, and thermal management. Experience with high-speed digital, analog, RF, and mixed-signal board designs. Familiarity with IPC standards and controlled impedance design. Experience in designing high-density boards that incorporate microcontroller, mixed-signal circuits, and peripherals such as Ethernet, USB, I2C, SPI, DDRx, etc. Solid knowledge in the board fabrication process. Strong communication skills to interact with colleagues, peers, and stakeholders in Global Engineering centers. Able to work efficiently independently as a team member and have the capacity to work on tight deadlines with high efficiency. Self-learner, able to work with autonomy, readiness for foreign/domestic travel for short/long-term basis. Excellent communication and project management skills. Nice to Have: Experience in Altium tool, Experience with Valor NPI or similar DFM tools.,

We are seeking a Director of Engineering (Design Verification) to oversee and expand our DV practice. With over 15 years of experience in SoC/ASIC verification, exceptional technical expertise, demonstrated leadership abilities, and the talent to motivate high-performing teams, you will play a pivotal role in our organization. Responsibilities include leading end-to-end SoC/ASIC Design Verification programs, establishing DV methodologies, flows, and best practices (UVM, SV, C-based), delivering technical leadership and practical problem-solving, managing and guiding top-performing engineering teams, collaborating with cross-functional teams for project success, driving customer engagement, ensuring delivery excellence, and supporting business development through pre-sales and technical discussions. The ideal candidate will possess a minimum of 15 years of semiconductor design verification experience, including at least 5 years in a leadership capacity. Proficiency in SystemVerilog, UVM, C/C++ co-simulation, and testbench architecture is essential. In-depth knowledge of ARM architecture, AMBA protocols (AXI, CHI, APB), high-speed interfaces (PCIe, DDR, Ethernet), Formal Verification, GLS, coverage closure, GLS methodology/flows, VIP Integration & Sequence usage, C-SV co-simulation, and Python scripting is required. Strong skills in people management, mentoring, and stakeholder engagement are also critical. Joining Seminovaa offers you the chance to be part of a rapidly growing semiconductor services company, led by its founder. You will have the opportunity to shape and lead the Design Verification practice, working on cutting-edge projects in AI, Automotive, Networking, and High-Performance Computing. Our collaborative, innovation-driven culture provides global exposure and a dynamic work environment. Apply now by sending your profile to careers@seminovaa.com. #SemiconductorJobs #VLSICareers #ChipDesign #NowHiring #Seminovaa #DFTengineers #Verificationengineers #PhysicalDesignEngineers,

As a skilled and experienced Digital Circuit Design Engineer, your primary responsibility will be leading the design, development, and validation of high-performance digital systems. You should have expertise in digital logic design, proficiency with HDL languages and FPGA tools, and a strong grasp of embedded systems integration. Your key responsibilities will include designing and implementing complex digital circuits such as logic gates, finite state machines, and synchronous/asynchronous architectures. You will utilize industry-standard tools like Verilog, VHDL, and FPGA development environments for simulation, synthesis, and verification. Additionally, integrating digital designs with communication and memory protocols like PCIe, DDR, UART, USB, and SPI will be crucial. In this role, you will be expected to conduct thorough testing, debugging, and optimization of digital systems. Collaboration with firmware and embedded software teams using C/C++ or Python for system-level integration will also be a significant part of your job. To qualify for this position, you should hold a B.Tech/M.Tech degree in ECE/Embedded Systems/Digital Electronics and possess a minimum of 3 years of relevant experience.,

About our Group: Intel NEX team is responsible for delivering top-notch Ethernet products and plays a pivotal role in Intel's transition from a PC-centric company to a key player enabling the cloud and a multitude of smart, interconnected computing devices. Our Ethernet products are instrumental in moving global data and serve as the backbone for cloud services and telecommunications data centers. We are a team of problem-solvers, trailblazers, and visionaries committed to developing network technologies that are currently leading and reshaping data center ecosystems. As a globally acclaimed organization, we are in search of exceptional individuals to drive our growth during this exciting phase in Ethernet networking technology. If you are ready to embark on this journey, we invite you to join us. We are looking for a highly motivated, dynamic, team-oriented engineer with 4-8 years of relevant experience, eager to undertake the challenge of overseeing IP, Subsystem, and SoC Pre-Silicon verification for the latest cutting-edge products within the Ethernet Product Group at Intel. In this role, you will be involved in leading and participating in the verification of IP, Sub-systems, and SoC. Your main focus will be on executing pre-Silicon validation plans in alignment with the IP/product release schedule and deliverables, conducting debugging, reporting failures, identifying potential failures, and assisting in determining the root cause of failures. You will be responsible for creating/reviewing verification test plans, engaging in discussions across various domains to gain a comprehensive understanding of requirements, designing the architecture and verification environment in UVM for pre-silicon RTL verification, developing/running/debugging tests in System Verilog, mentoring other engineers in utilizing the verification infrastructure and constructing test benches. Your tasks may include participating in block/subsystem/SoC level testing, contributing to functional coverage, code coverage reviews, and implementing feedback. Additionally, you should be equipped to provide support for post-silicon/platform failures related to the IP provided. Timely goal achievement, highlighting issues and obstacles to management promptly, and collaborating with teams across diverse locations are key aspects of this role. Minimum Qualifications: Bachelors/Masters degree in Electrical, Electronics, or Computer Science streams. Relevant Experience: 3 to 8 Years. Preferred Skillset: Proficiency in UVM with the ability to architect complex testbenches and verification infrastructure, adept at debugging and issue resolution. Familiarity with protocols such as AXI, AHB, APB, ACE, AXI Stream, foundational knowledge of A-profile Cores, and expertise in Networking Protocols like PCIe, Ethernet, RDMA, NVME, or experience in DDR will be highly advantageous. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Business Group: The Network & Edge Group amalgamates network connectivity and edge into a business unit committed to driving end-to-end product leadership in technology. Its portfolio encompasses leading products in Ethernet, Switch, IPU, Photonics, Network, and Edge that are of paramount importance to our clientele. *Please note that job posting details (such as work model, location, or time type) are subject to change.,

X-PHY is a leading cybersecurity technology company that specializes in providing advanced solutions to safeguard businesses against emerging cyber threats. As a hardware-based cybersecurity firm, our focus is not just on creating products but on shaping the future of cybersecurity. We are on a mission to redefine industry standards, push boundaries, and develop transformative solutions that protect the digital world. Joining our team means embarking on an entrepreneurial journey where you have the opportunity to not only work for the company but to grow alongside it. We are seeking individuals who are visionary thinkers, bold strategists, and decisive doers. We are looking for people who are ready to challenge conventional norms, drive innovation, and be part of something transformative. If you are passionate about shaping the future of cybersecurity, this is your chance to make a difference at X-PHY. Currently, we are looking to hire a Senior Firmware Engineer to assume the role of Team Lead for our firmware group. This position involves a combination of hands-on embedded firmware development, technical leadership, and strategic oversight. As the Team Lead, you will be responsible for leading a dedicated team in designing, developing, and optimizing firmware for our cutting-edge cybersecure hardware products. You will collaborate closely with cross-functional teams, including hardware, FPGA, and cybersecurity engineers, to deliver secure, high-performance, real-time firmware systems on ARM and FPGA-based platforms. **Key Responsibilities:** - Lead the firmware development lifecycle, from architecture and design to implementation, validation, and deployment. - Guide and mentor junior engineers, perform technical reviews, and help enhance team capabilities. - Design, develop, and maintain low-level firmware and device drivers for ARM and FPGA-based embedded platforms. - Collaborate with hardware and FPGA engineers to define system architecture and interface layers. - Work on secure boot processes, BSPs, and diagnostic firmware for secure SSDs and other hardware. - Implement cybersecurity measures such as encryption, secure key storage, and tamper detection in firmware. - Oversee firmware testing infrastructure, including unit testing, integration testing, and CI support. - Interface with other engineering leads to align schedules, requirements, and product goals. - Contribute to system performance tuning and optimization. - Stay updated with best practices in embedded security, real-time processing, and secure firmware updates. **Qualifications:** - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline. - 7+ years of experience in firmware or embedded software development, with at least 2 years in a technical leadership role. - Proficient in C/C++, with additional experience in Python for scripting and testing. - Strong experience with ARM architectures and SoC platforms. - Expertise in firmware-hardware interaction, device drivers, memory-mapped I/O, and BSPs. - Experience developing for and integrating with FPGAs using Verilog/VHDL. - Deep understanding of real-time operating systems and/or embedded Linux environments. - Familiarity with hardware protocols including PCIe, I2C, SPI, UART, and DDR. - Hands-on debugging experience using tools such as JTAG, oscilloscopes, and logic analyzers. - Proven ability to lead complex technical projects across multiple teams. **Preferred Qualifications:** - Experience with secure embedded systems, cybersecurity principles, and threat models. - Familiarity with AI/ML deployment on embedded platforms. - Experience with Git-based workflows, CI/CD pipelines, and build systems. - Experience with NVM systems and custom SSD firmware development. Please note that this is a full-time, onsite role based in Singapore. Only candidates currently based in Singapore or willing to relocate will be considered. **Benefits:** - Performance Bonus: Competitive bonuses tied to high performance. - Restricted Stock Units (RSUs): Stake in the company's success. - Career Advancement Opportunities: Clear career progression pathways. - Collaborative Work Environment: Innovation, collaboration, and continuous improvement are valued.,

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team in Bangalore/Hyderabad, India, contributing to cutting-edge technological work in the field of integrated circuits. Your expertise will be crucial in driving the design and verification efforts for complex IP/Subsystem/SoC blocks. Design Lead: In the role of RTL Design Lead, you will be responsible for ensuring bug-free RTL from requirements or specifications. Your experience in multiple tape-outs and driving the design effort for complex blocks will be instrumental in the success of our projects. Verification Lead: As a Verification Lead, your role will involve catching bugs and ensuring that the design intent is met. Your expertise in leading multiple tape-outs and closing the verification of complex blocks will be essential in delivering high-quality results. For the Design role, we are looking for a Senior RTL Subsystems Designer Lead with a minimum of 8 years of experience. You should be able to drive the Subsystem life cycle from requirements to final release phases, work on defining micro-architectures, coding RTL with best practices, and collaborate with cross-functional teams to drive projects to completion. Key skills required for the Design role include proficiency with standard protocols such as PCIe, DDR, UFS, USB, AMBA, hands-on experience with low power design, understanding of DFT requirements and architecture, and the ability to work effectively with cross-functional teams. For the Verification role, we are seeking a Senior Verification Lead with a minimum of 8 years of experience. You should be able to drive the complete Verification cycle, including crafting test plans, architecting verification environments, developing test infrastructure, and driving closure with coverage. Key skills required for the Verification role include proficiency with Functional Verification of standard protocols such as PCIe, DDR, UFS, USB, AMBA, power-aware Verification with UPF, gate-level verification hands-on experience, and the ability to work effectively with cross-functional teams to drive projects to completion. If you are passionate about pushing the boundaries of technology and working on challenging projects in the SysMoore era, we invite you to join our dynamic team at Synopsys and contribute to the exciting world of integrated circuit design and verification.,

As a Senior/Lead/Sr. Lead Design Verification Engineer at our company located in Bangalore or Hyderabad, you will play a crucial role in ensuring the verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. You will need to have a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with a minimum of 4 years of hands-on experience in this domain. Your responsibilities will include utilizing your expertise in SystemVerilog and UVM to develop verification components like scoreboards, monitors, and sequencers. You will be required to have a strong understanding of digital design principles, verification methodologies, and simulation tools. Additionally, familiarity with protocol specifications and industry standards for DDR, PCIe, UCIe, or NVMe will be crucial for this role. Having experience with simulation tools such as VCS, ModelSim, or Questa will be an added advantage. You should also possess good debugging skills using tools like Waveform Viewers, Logic Analyzers, and protocol analyzers. Problem-solving skills, attention to detail, and the ability to work collaboratively are essential traits for this position. Preferred qualifications for this role include experience with formal verification techniques, knowledge of interface protocols like USB, Ethernet, or SATA, and proficiency in scripting languages like Python for automation purposes. Familiarity with FPGA-based verification platforms and hardware debugging tools will be beneficial in excelling in this role. If you are looking to join a dynamic team where you can leverage your skills in design verification and work on cutting-edge technologies, this position is ideal for you. Join us in our mission to push the boundaries of innovation and make a significant impact in the field of high-speed interface verification.,

You are in search of an experienced senior verification engineer with over 10 years of expertise in ASIC/SOC/IP/block level functional verification utilizing system verilog/UVM. The perfect candidate for this role should possess a comprehensive understanding of UVM, advanced UVM, and system verilog. Your main responsibilities will include developing a detailed test plan, constructing a complete test-bench, and creating a robust verification environment that comprises interface agents and scoreboard in UVM. Additionally, you should have in-depth knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB. Strong debugging skills are essential to promptly address test-bench issues and failures. As part of this role, you will be accountable for verification closure by focusing on coverage and managing bug reports. Proficiency in utilizing industry-standard verification tools like Questa, VCS, or ModelSim is required. Experience with scripting languages like python, perl, or TCL for automation tasks is also beneficial. Furthermore, you will be responsible for managing a team of 6 to 7 Engineers and engaging with customers to provide task updates. Experience in collaborating with Japanese customers is a prerequisite for this position. Proficiency in the Japanese language is a mandatory skill. If you meet these qualifications and are enthusiastic about taking on these responsibilities, we encourage you to apply for this challenging and rewarding role.,

As a Hardware-Assisted Verification Expert at Synopsys, you will play a crucial role in bridging and closing gaps between Emulation IP features and Design IP verification for both Controller and PHY functions. Your deep knowledge of IP interfaces like PCIe and DDR, coupled with experience in platforms such as Zebu, HAPS, and EP, will be essential in driving requirements for Emulation IP and ensuring its correct deployment in verification strategies. Your hands-on approach and collaborative mindset will drive innovation in defining requirements for IP product development in the context of emulation. Your responsibilities will include reporting metrics, driving improvements in Emulation IP, ensuring test plans deliver required function and quality, and staying ahead of evolving standards. You will enhance cross-functional collaboration, change the validation mindset in using Emulation IP for digital designs, and evolve best-in-class methodologies within the organization. Your impact will be felt in improving product quality, driving innovation, and standardizing workflows to increase efficiency and compliance. To excel in this role, you should have 10+ years of relevant experience, a results-driven mindset, exposure to advanced protocols like PCIe and DDR interfaces, and a proven track record in IP product development, particularly in emulation. Your excellent communication skills, adaptability, and comfort in a matrixed, international environment will be key in driving success in this position. Join us at Synopsys to transform the future through continuous technological innovation.,

You will be joining Eximietas as a Senior Design Verification Engineer/Lead in Bengaluru with 5-15 years of experience. Your primary responsibility will be to lead the SoC Design Verification efforts for complex projects, ensuring the successful execution of verification plans. This includes developing and implementing comprehensive verification strategies for high-speed and low-speed peripherals such as I2C, SPI, UART, GPIO, QSPI, as well as high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR, HBM. You will be conducting Gate-level simulations and power-aware verification using tools like Xprop and UPF. Collaboration with cross-functional teams, including architects, designers, and pre/post-silicon verification teams, will be crucial to ensure alignment and seamless integration of verification efforts. Your role will involve analyzing and implementing System Verilog assertions and functional coverage to ensure thorough verification of design functionality. Mentorship and technical guidance to junior verification engineers will be part of your responsibilities to elevate team performance. Leading and managing a dynamic team of verification engineers, fostering a collaborative and innovative work environment will be essential. You will also ensure that all verification signoff criteria are met, with clear and comprehensive documentation. Your dedication, work ethic, and commitment to meeting project goals and deadlines will be vital. Upholding quality standards and implementing best test practices to contribute to continuous improvements in verification methodologies will also be expected. You will work with verification tools from Synopsys and Cadence, including VCS and Xsim, and integrate third-party VIPs (Verification IP) to enhance verification coverage. To qualify for this role, you should have 5+ years of hands-on experience in SoC Design Verification and expertise in verification of high-speed SoCs and various protocols. Proficiency in System Verilog for verification, gate-level simulations, and power-aware verification using Xprop and UPF are necessary. Strong hands-on experience with VCS and Xsim from Synopsys and Cadence, mentorship experience, and demonstrated ability to work with cross-functional teams are also required. A strong understanding of verification methodologies and the ability to contribute to their continuous improvement are essential.,

As a Principal Software Engineer at Cadence, you will have the opportunity to work on cutting-edge technology in an environment that encourages creativity, innovation, and making a real impact. Cadence, a pivotal leader in electronic design, with over 30 years of computational software expertise, is seeking a candidate to join their highly talented team in Bangalore or Ahmedabad. In this role, you will be responsible for developing, implementing, and testing features for the next generation of verification IP tools. The ideal candidate should have excellent communication skills, the ability to quickly ramp up on new technologies independently, and a strong background in functional verification using SV/UVM. Additionally, hands-on knowledge of Python/Scripting, experience with memories such as HBM, LPDDRR, GDDR, and DDR, as well as prior VIP usage and development experience would be advantageous. Cadence offers an employee-friendly work environment that focuses on the physical and mental well-being of its employees, career development, learning opportunities, and celebrating success. The company's unique One Cadence - One Team culture promotes collaboration to ensure customer success, while providing avenues for learning and development based on individual interests and requirements. Qualifications for this role include a BE/BTech/ME/MS/MTech in Electrical/Electronics or equivalent, along with strong analytical and communication skills. The successful candidate should be self-motivated, possess strong written, verbal, and presentation skills, and have the ability to establish close working relationships with both customers and management. Creativity, the willingness to explore unconventional solutions, and the ability to work effectively across functions and geographies are essential behavioral skills required for this position. Join Cadence and be part of a diverse team of passionate individuals dedicated to making a difference in the world of technology. If you are ready to work in a supportive and friendly environment where innovation and collaboration are valued, we encourage you to apply for the Principal Software Engineer position by sending your CV to kmadhup@cadence.com. Regards, Madhu,

As a Senior Design/Verification - Subsystems Lead at Synopsys, you will be part of the Digital IP Subsystem team that has experienced significant growth. We are seeking talented engineers to join us in Bangalore/Hyderabad, India and be a part of our exciting journey in the SysMoore era. **Design Lead:** In the role of an RTL Design lead, you will experience the thrill of achieving bug-free RTL from requirements or specifications. Your expertise in driving the design effort for complex IP/Subsystem/SoC blocks, with a track record of multiple tape-outs, will be invaluable in delivering high-quality results. **Verification Lead:** As a Verification lead, you will enjoy the challenge of identifying and rectifying bugs to ensure the design intent is realized. Your role is critical in ensuring the flawless operation of chips, such as those on space telescopes capturing stunning images of galaxies. Your experience in leading multiple tape-outs and closing verifications of complex IP/Subsystem/SoC blocks will be instrumental in our success. **Design role:** In the position of a Senior RTL Subsystems Designer Lead with over 8 years of experience, you will be responsible for driving the Subsystem life cycle from requirements to final release phases. This includes crafting functional specifications, defining micro-architectures, coding RTL using best practices, conducting RTL quality checks, collaborating with Verification and implementation teams, and overseeing project completion. Proficiency in standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as hands-on experience in low power design and understanding of DFT requirements and architecture are essential. Your ability to work effectively with cross-functional teams will be crucial in delivering successful projects. **Verification role:** In the role of a Senior Verification lead with over 8 years of experience, you will lead the complete Verification cycle by crafting test plans, architecting verification environments, developing test infrastructure, and executing plans to closure with coverage. Proficiency in Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA, as well as power-aware Verification with UPF, is required. Hands-on experience in Gate Level Verification is a valuable addition. Your collaboration with cross-functional teams will be key to driving projects to completion.,

You are a highly experienced ASIC RTL Design Architect responsible for leading the design and verification of cutting-edge SoCs and high-speed digital IPs. With over 10 years of experience in ASIC/FPGA design, your expertise lies in RTL using Verilog/SystemVerilog, Lint, CDC, and Spyglass-based design verification methodologies. Your main responsibilities include leading RTL design and micro-architecture for high-performance ASIC SoCs, ensuring compliance with Lint, CDC, and SDC constraints using Spyglass or equivalent tools, driving design optimization and timing closure, as well as collaborating with cross-functional teams such as Design Verification, DFT, Physical Design, and Software teams. You will also be involved in developing and reviewing architecture specifications, coding guidelines, and best practices, as well as performing synthesis, timing analysis, and static verification using tools like STA, LEC, and Formal Verification. Key requirements for this role include a minimum of 10 years of experience in ASIC RTL design and architecture, expertise in Verilog/SystemVerilog for RTL design, strong knowledge of Spyglass Lint/CDC and static verification methodologies, experience in SoC micro-architecture, high-speed interfaces, and power optimization. Additionally, you should have a solid understanding of synthesis, STA, timing closure, backend constraints, experience with EDA tools like Synopsys, Cadence, Mentor Graphics, and familiarity with UVM-based verification and scripting languages such as TCL, Python, or Perl. Preferred qualifications include an M.Tech/MS/PhD in Electrical Engineering, Computer Engineering, or related field, experience in chip tape-out and production silicon, and an understanding of hardware security, reliability, and safety standards. If you are looking to be part of a team that is shaping the future of high-performance computing, apply now and join us in building innovative solutions together.,