211 Ddr Jobs - Page 4

We are seeking experienced Senior/Lead ASIC Verification Engineers to join our Noida-VIP team. With 5 to 15 years of experience in Verification, particularly using industry-standard protocols and methodologies, this role offers a challenging opportunity for individuals well-versed in System Verilog, Verilog, and Object-Oriented Programming. As a successful candidate, you will have demonstrated your ability to lead the development of reusable Verification environments on at least 2 projects using VMM, OVM, or UVM methodologies. Your expertise should extend to protocols such as UCIe, PCIe, CXL, Unipro, USB, MIPI, HDMI, Ethernet, DDR, LPDDR, and HBM memory. Your responsibilities will include contributing to the development of the VIP, reviewing and signing off on VIP development and updates, and collaborating with Architects and methodology experts to address issues and drive architectural and methodological perspectives. If you are a proactive and reliable professional with a passion for Verification, we invite you to share your updated CV with us at taufiq@synopsys.com. Feel free to refer anyone who may be interested in this exciting opportunity as well. At Synopsys, we value Inclusion and Diversity, considering all applicants for employment without regard to race, color, religion, national origin, gender, gender identity, age, military veteran status, or disability. Join us in shaping the future of technology.,

Qualcomm India Private Limited is looking for a Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other systems to develop cutting-edge products. You will work in collaboration with cross-functional teams to develop solutions that meet performance requirements. To be eligible for this position, you should have a Bachelor's degree, Master's degree, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field, along with relevant work experience. The ideal candidate will have a solid understanding of Electronics engineering fundamentals, DDR, and High-Speed IO circuit analysis techniques, as well as semiconductor manufacturing processes. As a part of the Post Silicon Engineering group at Qualcomm, you will be responsible for developing test strategies and executing Bench characterization for LPDDR & PCDDR Subsystem components and High-Speed IO interfaces. You will drive first Silicon debug, evaluate semiconductor fabrication processes, and perform failure analysis to address design issues. Additionally, you will work with global teams in a time-critical environment. The desired candidate should have hands-on experience with Bench instruments such as oscilloscopes, network analyzers, and logic analyzers. Proficiency in writing and debugging test code using languages like C, C#, or Python is required. Knowledge of CAD software such as Mentor Graphics DA or Cadence Allegro would be a plus. Effective communication skills, both verbal and written, are essential for this role. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. If you are interested in this role or need more information, please contact Qualcomm Careers.,

As a Systems Architecture Lead, you will be responsible for the development of systems and product architecture for advanced Application Processors. Your role will involve collaborating with hardware engineering, software engineering, application/solutions engineering teams to design and create scalable, robust solutions for our advanced microprocessor products targeting Industrial, IOT, and Automotive Edge markets. A deep technical understanding of MPU HW & SW architecture, Solutions Engineering, Use Case Analysis, Validation, Optimization, and system integration is essential for this role. Your key responsibilities will include driving the definition and development of MPU architecture in alignment with market trends and industry standards. You will work closely with product marketing teams and customers to translate requirements into detailed specifications. Furthermore, you will be responsible for defining scalable computing architectures, integrating security mechanisms, collaborating with cross-functional teams, and optimizing power and performance benchmarks. To qualify for this role, you should hold a Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field with 15 years or more of relevant experience. Additionally, experience in use-case analysis, Linux, Zephyr, Free RTOS or similar operating systems, microprocessor and microcontroller architectures, system-level performance optimization, low-power design, SW/HW co-design, and real-time processing is required. Strong collaboration skills and familiarity with high-speed interconnects, memory architectures, bus protocols, and product development processes are also necessary. Preferred qualifications include experience with ARM Cortex and/or RISC-V architecture, media processing, vision and imaging applications, system-level simulation tools, Machine Learning Hardware IPs, functional safety, and security standards. Familiarity with Wi-Fi integration, networking protocols, and secure wireless communication would be advantageous. In this role, you will play a crucial part in designing and developing cutting-edge solutions for advanced microprocessor products, contributing to the success and innovation of our products in Industrial, IOT, and Automotive Edge markets.,

As a Systems Engineer at Qualcomm India Private Limited, you will be part of the Platform Architecture Team working on next-generation System-on-chip (SoC) for various product categories like Compute, smartphone, and IoT. You will collaborate with Hardware and Software teams to understand design requirements, specifications, and interface details. Your responsibilities will include validating architecture/microarchitecture models, integrating models to the SoC platform, and performing area, power, and performance trade-offs analysis. You will develop system level architecture and microarchitecture of system use-cases, working closely with cross-functional teams. Minimum qualifications for this role include a Bachelor/Masters Degree in Electronics & Communication / Micro Electronics or related field with 5+ years of Physical Design experience, or a PhD in the same field with 2+ years of experience. Ideal candidates should have a good understanding of SoC Design & Physical Design Concepts, VLSI flow, digital design, computer architecture, and HDL languages. Proficiency in Scripting languages like Perl/Tcl/Python is preferred. Knowledge of ARM architecture, power management fundamentals, and communication skills are essential. Candidates with expertise in Physical Design flow, ARM and RISC-V Architecture, DSPs, CPUs, DDR, Interconnect, System Cache, and power/performance analysis will be preferred. A Bachelor's/Master's/PhD in Engineering, Information Systems, Computer Science, or related field with relevant work experience is required. Qualcomm is an equal opportunity employer committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you are seeking more information on this role, please contact Qualcomm Careers.,

As an Analog Design Engineer at Sykatiya Technologies, you will be an integral part of our highly talented team that focuses on Technical Ability and a positive Attitude. Your contributions to projects will reflect our commitment to excellence for our customers. Our team consists of skilled engineers and experts in Design Verification, DFT/Test, Physical Design, and Analog Design for ASICs. We are looking for an Analog Design Engineer with 3-12 years of experience to join our team in Bangalore. The ideal candidate will have experience in transceiver design for high-speed interfaces such as DDR, HBM, PCIe, USB3, and JESD204. Exposure to nodes below 22nm is a plus, along with experience in FINFET technology and the 32G-112G range of SERDES. In this role, you will be responsible for taking at least one block from circuit design to layout closure. You should also be able to guide the layout team in high-performance matched circuit design. Understanding reliability requirements such as ESD, EMIR, EOS, Aging, and being able to work independently while mentoring junior team members are essential qualities we are looking for. If you have exposure to post-silicon validation, it would be considered a plus. Join us at Sykatiya Technologies and be part of a dynamic team that values technical expertise, a positive attitude, and a commitment to excellence in Analog Design.,

About Us: Silcosys Solutions Private Limited is a pioneer in semiconductor innovation, committed to delivering cutting-edge analog design solutions that power the future of technology. If you are eager to work on impactful projects and advance your expertise, we invite you to join our dynamic team. Job Description: As an RTL Design Engineer, you will be responsible for designing and implementing high-quality RTL code for complex digital blocks and subsystems. You will collaborate with architects, verification, and physical design teams to create designs that meet functional, performance, and power requirements. Responsibilities: Develop RTL designs for digital IPs, subsystems, and SoCs based on architectural specifications. Collaborate with architects and system engineers to translate high-level requirements into detailed micro-architecture. Perform design optimizations for area, power, and performance. Conduct design reviews and ensure compliance with coding standards and best practices. Work closely with verification teams to develop test plans and ensure 100% functional coverage. Debug and resolve design and integration issues during simulation and post-silicon validation. Participate in timing analysis and closure in collaboration with the physical design team. Document design specifications, test cases, and user guides for IP and SoC designs. Requirements: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or related field. 2-10 years of experience in RTL design and implementation for VLSI systems. Strong expertise in Verilog, SystemVerilog, and RTL design methodologies. Solid understanding of digital design concepts such as pipelining, clock domain crossing, and low-power design techniques. Experience with EDA tools like Synopsys Design Compiler, Cadence Genus, or equivalent. Proficiency in scripting languages (Python, Perl, TCL) for design automation. Familiarity with SoC interfaces and protocols like AXI, AHB, PCIe, USB, or DDR. Experience in static timing analysis (STA) and timing closure workflows. Strong problem-solving skills and the ability to debug complex design issues. Excellent communication and collaboration skills to work effectively in a team environment. Preferred Qualifications: Experience with low-power design and multi-clock domain systems. Knowledge of advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. Exposure to formal verification methodologies. Experience in hardware-software co-design and FPGA prototyping. Familiarity with machine learning or AI-based RTL optimizations. Why Join Us Work on groundbreaking projects in VLSI design and technology. Collaborate with a team of industry experts in a supportive and innovative environment. Opportunities for career growth and continuous learning. Competitive salary and benefits. How to Apply: If this role excites you, submit your updated resume at info@silcosys.com and any relevant project portfolios today. Join Silcosys Solutions Private Limited and shape the future of analog design!,

We are actively hiring multiple Design Verification (DV) Engineers for Bangalore (hybrid model). If youre looking for a new challenge and can join quickly, youll be among our top-priority candidates! Open Positions : 1. DV Engineer GLS / UVM / SystemVerilog / CDC Experience : 3–8 years Skills : Gate-Level Simulations, UVM testbench development, CDC verification, timing-aware verification 2. DV Engineer – PCIe / DDR / UVM / SV Experience : 4–18 years Skills : Protocol-level verification, PCIe or DDR, UVM, SystemVerilog 3. DV Engineer – UVM / SystemVerilog Experience : 5–10 years Skills : Testbench architecture, functional verification, scalable UVM environments

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards Skills Must have 5-12 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

Design Verification Engineer - Specialised in Protocol like; PCIe/Ethernet/DDR/LPDDR/HBM Location: Noida, UP / Bangalore, India Experience: 3-10 Years Job Description: Experience in interconnect protocol PCIe/ Ethernet. Experience in Memory protocol DDR/LPDDR/HBM; HBM is preferred. AXI/ACE/CHI understanding, [AXI is must] Understanding of DMA usage. Strong in SV/UVM. Experience in the usage of standard VIP in TBs (preferably Synopsys) AI/ML network understanding (good to have). Additional knowledge of perl/tcl scripting will be an advantage. Must Bachelors Degree in Electrical, Electronics or Computer Engineering

Develop verification testbench components for chip/module level using System Verilog, C/C++. Use Verification methodologies (Object oriented, UVM etc) to develop extendable test-bench/test-cases environment. Define and execute detailed verification plan from spec working with architects, designers, system engineers. Write tests, Debug tests, automate regression scripts and regression environment. Incorporate code-coverage, functional coverage, assertions, cover-groups etc to achieve 100% verification completeness prior to tapeout. Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required. Excellent debugging skills in both SW and ASIC hardware. Must be good in building verification environments preferably using Verilog, System Verilog, UVM, C/C++/PLI etc. Proficiency in scripting language like Perl, Tcl/Tk, Shell is a definite plus. Experience with simulators like ncVerilog (Incisive), VCS, Eldo and debug tools like Verdi/Debussy. Good understanding of latest formal verification techniques, assertions, properties is a plus. Understanding or prior experience with Industry standard protocols like USB/SPI/SATA/Ethernet/DisplayPort/SRIO/DDR/PCIE/DDR4/LPDDR4/DFI etc is a definite plus. Understanding or Prior Experience in ARM/Tensillica Processor platforms is a definite plus. Good written and oral communication skills. Ability to clearly document plans.

Electronics Hardware Lead Bachelor’s or master’s degree in electrical engineering, Electronics Engineering, or related field. • Min 10 Yrs of expnc in electronics H/w design, preferably with a focus on inertial navigation or aerospace apps.

Qualcomm India Private Limited is a leading technology innovator that strives to push the boundaries of what is possible, enabling next-generation experiences and driving digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge products. Collaboration with cross-functional teams will be essential to develop solutions and meet performance requirements. To be eligible for this position, you should have a Bachelor's/Master's/PhD degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with relevant work experience ranging from 4 to 6+ years. Join Qualcomm's design verification team and be involved in verifying high-speed mixed-signal IP designs for products targeted for 5G, AI/ML, compute, IoT, and automotive applications. Responsibilities will include defining test plans, developing testbenches using advanced verification methodologies, authoring assertions, developing test cases, and collaborating with various teams to ensure successful verification and integration. Qualified candidates should possess a Master's/Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with at least 12+ years of ASIC design verification experience. Knowledge of HVL methodologies like SystemVerilog/UVM and experience with ASIC simulation/formal tools are required. Preferred qualifications include experience with low power design verification, formal verification, gate-level simulation, knowledge of standard protocols, scripting languages like Python or Perl, and experience with mixed-signal IP design verification. Qualcomm is an equal opportunity employer that is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Additionally, Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. For more information about this role, please contact Qualcomm Careers.,

NK Securities Research is a leading financial firm that leverages cutting-edge technology and sophisticated algorithms to trade the financial markets. Founded in 2011, we have gained invaluable experience in the field of High-Frequency Trading across different asset classes. As an FPGA Developer at NK Securities Research, your primary responsibility will be to design, implement, and rigorously test RTL (Register-Transfer Level) designs to power our high-frequency trading strategies. Your contributions will be instrumental in reducing system latency and enhancing performance, directly influencing trading outcomes. You will be tasked with developing high-performance RTL designs using VHDL or Verilog for FPGA-based systems, optimizing hardware implementations for ultra-low latency and high throughput, and ensuring thorough functional and timing testing of RTL designs to meet specifications. Additionally, you will be responsible for debugging and resolving issues using FPGA debugging tools such as SignalTap, ChipScope, or ModelSim. Collaboration with hardware and software teams to seamlessly integrate FPGA solutions with the Software Trading Stack will be a key aspect of your role. Maintaining clear and comprehensive documentation of designs, test cases, results, and benchmarks is essential to ensure effective communication and knowledge sharing within the team. Preferred qualifications for this role include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field from top IITs. Proficiency in VHDL or Verilog/SystemVerilog, hands-on experience with industry-standard tools like Xilinx Vivado, expertise in writing testbenches and conducting simulation-based verification, familiarity with static timing analysis, and proficiency in debugging tools such as SignalTap, ChipScope, or ModelSim are desired. Exposure to high-speed interfaces like PCIe, Ethernet, or DDR, as well as a basic understanding of low-latency design principles and architecture, are considered advantageous. Candidates with a proven track record in delivering high-quality RTL designs, strong analytical and problem-solving skills, and the ability to work independently while collaborating effectively in a team environment are encouraged to apply. In return, NK Securities Research offers a competitive salary package, the opportunity to work in a dynamic and collaborative environment, career growth and development opportunities, catered breakfast and lunch, an annual international trip, and monthly team dinners.,

SoC Verification Engineer SoC Verification Engineer >> SoC Verification Engineer Post SoC Verification Engineer Required Experience 1 to 3 years Location: Bangalore,Delhi NCR,Hyderabad Openings 8-10 Education BE/B.Tech./MS/M.Tech.(Electronics or Electronics & Communication) Must haves: Worked on IP level verification environment 1 to 3 years of experience Good experience with Verilog, System Verilog and UVM Experience with verification for protocols like AXI or AHB Experience with any of the following protocols: DDR, PCIe, Ethernet, MIPI, USB Excellent Team Player Good To Have Experience of SOC Verification Experience of Formal verification Experience on verification of automotive protocols Email your resume to careers@truechip.net and mention position/location in the subject,

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: You will be part of Automotive System Performance team that is responsible for profiling and optimizing the System Performance on Snapdragon Automotive chipsets. Responsibilities include: Drive Performance analysis on silicon using various System and Cores (i.e. CPU, GPU, Memory and AI/ML) benchmarks like Dhrystone, Antutu, GeekBench, GFXBench, SPECInt, ResNet50 etc. Use of Performance tools to analyze the load patterns across IPs and identify any performance bottlenecks in system. Analyzing Performance KPIs of Auto SoC subsystems like CPU, GPU, NSP, Memory, Camera, Display, Video and corelate performance with projection Evaluate and characterize performance at various junction temperatures and optimize running at high ambient temperatures. Analyze and optimize the System performance parameters of SoC infrastructure like NoC, LP5 DDR, etc. Collaborate with cross-functional global teams to plan and execute performance activities on Auto chipsets as well make recommendations for next generation chipsets. Minimum Qualifications 7+ years of industry experience in the following: Experience working on any ARM/x86 based platforms, mobile/automotive operating systems and/or performance profiling tools. Experience in application or driver development in Linux\QNX and ability to create/customize make files with various compiler options is a plus. Must be quick learner and should be able to adapt to new technologies. Must have excellent communication skills. Preferred Qualifications Additional skills in the following areas are preferred: Knowledge of Computer architecture, LP5 DDR, Bus/NOC profiling is a big plus. Fundamentals on any Automotive operating system like AGL/QNX/Hypervisor & experience working on any Automotive applications. Basic Knowledge on any multimedia frameworks like OpenGL/ES, OpenMax and OpenCL is plus. Experience in creating professional quality reports and slides using MSOffice or any advanced visualization tools. Experience in PoC development and competitive analysis Knowledge on Voltage/Power/ Thermal domain is plus. Education RequiredBachelor's, Computer Engineering and/or Computer Science and/or Electrical EngineeringPreferredMaster's, Computer Engineering and/or Computer Science and/or Electrical Engineering Keywords Architecture Performance, System Performance, Automotive Performance, Benchmarks, Thermal Performance, UX optimization, QNX, Hypervisor, Application Development Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Software Engineer, you will design, develop, create, modify, and validate embedded and cloud edge software, applications, and/or specialized utility programs that launch cutting-edge, world class products that meet and exceed customer needs. Qualcomm Software Engineers collaborate with systems, hardware, architecture, test engineers, and other teams to design system-level software solutions and obtain information on performance requirements and interfaces. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field. Preferred Qualifications: Debug and Development of DDR init & run time driver sequences. Will be working on state-of-the-art DDR technology LP4x/LP5x. Opportunity to get the understanding of DDR technology. Will be responsible for driving multiple programs. Need to work on issues with multiple teams (performance, Phy, controller design etc.) Need to analyze lot of data and need to recognize patterns. Working on triage of the DDR issues. Test case enhancements and development Principal Duties and Responsibilities: Job description Minimum Qualifications The charter of the CoreBSP-DDR SW System team is to ensure that the end-product qualifies the defined acceptance criteria for DDR by meeting stability, Power, and Performance Goals . The team is looking for a candidate who has strong understating of system level test methodologies and run validations on mobile systems. The position involves Understanding of SOC Architecture and DDR SW Systems, identifying and debugging DDR systems issues ( memory corruptions, Memory Lock-ups, Bit flips, memory leaks etc..)reported by memory validation and also running system level validations tests. The engineer would have opportunity to interact with different SW & HW teams to understand DDR systems. The candidate is expected to own and drive multiple chipsets in DDR tech area. This position gives an exposure to understand various quality stages from product development to commercial launch of the product. Skills: C, Python, Embedded system , JTAG , processor architecture, RTOS operating system, core BSP driver level development and debug ,CPU architecture , SOC System knowledge. DesirableDDR technology Level of Responsibility: Works under supervision. Decision-making affects direct area of work and/or work group. Requires verbal and written communication skills to convey basic, routine factual information. Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively.

Job Specs : We are seeking a highly skilled and motivated ASIC Verification Engineer to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Verification IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location : Bangalore, Pune. Malaysia, Singapore Desired Profile : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering Visa / work permit sponsored for immediate hires Expertise in ASIC SOC verification Expertise in PCie Expertise in UVM, System Verilog and constrained random testing. Expertise in testbench architecture and SOC-level verification strategies. Expertise with protocols such as AXI, AHB, APB, USB, or DDR. Expertise with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa. Familiar with waveform debugging tools such as Verdi or DVE. Working knowledge of low-power verification (UPF) and DFT / scan concepts. Knowledge of scripting languages (Python, Perl, TCL) for automation. Good understanding of SoC architecture, including CPU subsystems, memory hierarchy, and peripherals. Job Specs : Develop and maintain full-chip verification environments using SystemVerilog UVM methodology. Define and execute test plans for SoC-level functionality, power intent (UPF), coherency, performance and interconnect protocols (e.g., AXI/ACE). Work closely with the RTL, DV, and integration teams to ensure complete coverage of functional and architectural features. Implement and manage stimulus generators, scoreboards, monitors, and checkers at full-chip level. Perform debugging, waveform analysis, and triage of failures in RTL simulations. Ensure code coverage and functional coverage goals are met and signoff criteria are satisfied. Collaborate with firmware/software and post-silicon teams to align verification efforts and resolve issues. Participate in formal verification, assertion-based verification, and low-power simulations. Support regression testing, issue tracking, and coverage closure. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Skills & Experience MTech/BTech in EE/CS with 7+ years of ASIC design experience. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5/6) is added advantage. Understanding of protocols like AHB/AXI/ACE/CHI is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Hands on experience in Low power SoC design is required. Responsibilities Mirco architecture & RTL development and its validation for linting, clock-domain crossing and DFT rules. Work with functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels. Hands on experience in constraint development and timing closure. UPF writing, power aware equivalence checks and low power checks. Support performance debugs and address performance bottle necks. Provide support to sub-system, SoC integration and chip level debug. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Preferred Qualifications: Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 8+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. 1+ year in a technical leadership role with or without direct reports. Principal Duties and Responsibilities: Leverages advanced Hardware knowledge and experience to plan, optimize, verify, and test critical electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates complex features and functionality into hardware designs in line with proposals or roadmaps for complex products. Conducts complex simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with cross-functional teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the novel manufacturing of solutions for leading edge products in the most advanced processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of critical materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Evaluates complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for complex Hardware projects. Level of Responsibility: Works independently with minimal supervision. Provides supervision/guidance to other team members. Decision-making is significant in nature and affects work beyond immediate work group. Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc. Has a moderate amount of influence over key organizational decisions.

3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipros Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc Deliver No.Performance ParameterMeasure1.Product design, engineering and implementationCSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards2.Capability development% trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs) Applications from people with disabilities are explicitly welcome.

Hands on experience in Circuit Design implementation of IPs including LDOs, Band Gap reference, Good working knowledgein Current Generators, POR, ADC/DACs, PLLs, Oscillators, Good working knowledge in General Purpose IOs, Temperature sensor, SERDES, PHYs, Good in Die to Die interconnect, High-speed IOs,

Hands-on experience in IP-level Design Verification using SystemVerilog and UVM. Strong in testbench architecture, assertions, coverage, and protocol checks. Good debugging skills and experience with regressions, simulations, and functional coverage. Required Candidate profile Strong hands-on in SV/UVM, IP-level testbench, coverage, assertions, and protocol verification. Proficient in debug, simulation tools, and regression handling. Self-driven, detail-oriented

Project description This is a great opportunity to work as a part of highly regarded team to deliver leading edge solutions. Responsibilities Drive the development of cutting-edge memory-related firmware projects, contributing to the creation of innovative solutions Collaborate with a highly regarded team to bring innovation to memory-related firmware, ensuring solutions are at the forefront of industry advancements Tackle complex challenges by employing strong problem-solving skills, enhancing firmware to meet evolving performance and reliability standards SkillsMust have 7-10 years' experience. Strong with C language programming Working knowledge of git/gerrit Good understanding of DDR4, DDR5, NVDIMM Good understanding of different DIMM types (UDIMM/SODIMM/RDIMM/LRDIMM/LPDDR) Good understanding of UMC features like ECC, SME, SEV, RAS etc Nice to have Understanding different vendor implementations and memory timing differences is a big plus

We are looking for Senior SOC Verification Engineers for the Hyderabad location. 1) SOC Verification 2) SV UVM 3) DDR, PCIe, Ethernet. Interested candidates, Kindly Share with me your updated profile with Naveen.a@modernchipsolutions.com

Strong in digital design. Skills in ASIC/FPGA verification(directed test or SV/UVM) A good knowledge of simulation flow. Good scripting knowledge Perl/python Share your Resume to mansoor@hisoltech.com

Hi all, We are hiring for the role ASIC Engineer HSIO Post-Silicon Electrical Validation Experience: 3 - 5 Years Location: Hyderabad Notice Period: Immediate - 15 Days Skills: We are seeking a skilled ASIC Engineer to join our High-Speed I/O (HSIO) Post-Silicon Electrical Validation team. The ideal candidate will possess hands-on experience with high-end lab equipment, proficiency in automation scripting, and a solid understanding of high-speed interfaces. This role involves validating and characterizing ASICs post-fabrication to ensure they meet performance, power, and reliability specifications Key Responsibilities Develop and execute detailed post-silicon validation plans for new ASICs. Design and implement test cases in Python, C++, LabView, or VBA for validating functionality, performance, and power metrics. Bring-up silicon in the lab and debug/resolve issues using high-end lab equipment such as oscilloscopes, JBERTs, and power supplies. Analyze and root-cause silicon failures, collaborating closely with design teams to drive resolution. Document validation results, prepare comprehensive reports, and communicate findings effectively to cross-functional teams. Required Qualifications Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 35 years of experience in post-silicon validation, hardware bring-up, or related fields. Proficiency in scripting languages such as Python, C++, LabView, or VBA for automation purposes. Hands-on experience with high-end lab equipment, including oscilloscopes, JBERTs, and power supplies. Strong understanding of high-speed interfaces like PCIe, DDR, and USB. Excellent analytical and problem-solving skills. Effective communication skills and the ability to work collaboratively in a team environment. If you are interested drop your resume at saraswati.g@acesoftlabs.com