211 Ddr Jobs - Page 5

Preparation of CMA, Ratio analysis study and understanding of credit appraisal note. Attending queries from Banks, Rating agency, ASM, Stock auditors, Internal Auditors & Stat Auditors etc. Understanding loan processing process (Working Capital- EPC, LC and Term Loan) and related technical requirement of Banks, Loan documentation and security perfection & satisfaction. Banking compliance (Stock statement, FFR/QMS, UFC etc.) Coordination with Banks for other operational issue. Clearance of EDPMS & IDPM related issues with Bank. Understanding of RBI & FEMA guideline and experience in foreign currency dealing SAP Functioning Interpretation of Financial Statement and analysis thereof MIS related to Banking & Treasury. Coordination with other team members for any operational issue Good knowledge of MS Office application i.e. MS Excel, MS Word, etc Only CA qualified will be considered working with Banking & Treasury team of mid size corporate with turnover of Rs 500cr to Rs 1000cr

Key Responsibilities : Lead and manage RTL design activities for complex ASICs, ensuring high performance and low power consumption. Integrating RTL components into System-on-Chip (SoC) designs Integrating RTL components into System-on-Chip (SoC) designs Architect and implement RTL for digital circuits (such as processors, communication systems, or custom IP cores). Mentor and guide junior RTL engineers in best practices for design, coding standards, and optimization techniques. Develop and refine RTL code in Verilog/SystemVerilog for ASIC development. Collaborate with cross-functional teams (Verification, Physical Design, and Software) to ensure successful integration of the ASIC design. Perform RTL design reviews, debugging, and optimization to meet design targets such as area, speed, and power. Work on creating micro-architectural specifications and ensure the design meets project requirements. Ensure designs are implemented with proper synchronization, timing constraints, and low power techniques. Participate in top-level design, integrating IP blocks, ensuring design consistency across subsystems. Drive the design flow from architecture and specifications through to implementation. Prepare and maintain technical documentation for designs and related processes. CDC, LINT and Integration expertise is expected. Required Skills & Experience : Bachelor's, Master's, or PhD in Electrical Engineering or related fields. 3-12 years of experience in RTL design for ASICs, with at least 3 years in a team lead role. Expertise in RTL design using Verilog or System Verilog. Solid understanding of digital design principles, including timing analysis, state machines, and pipelining. In-depth knowledge of ASIC design flow, from RTL to tape-out. Experience with EDA tools for synthesis, simulation, and timing analysis (e.g., Synopsys, Cadence). Strong debugging and problem-solving skills. Good knowledge on scripting (Python, Perl and Shell scripting) Knowledge of power, performance, and area (PPA) optimization techniques. Experience with designing for low-power, high-speed circuits is highly desirable. Excellent communication skills and the ability to work in a team environment.

About the Role This leadership position is pivotal within a global digital data business, contributing to the development of next-generation connectors, cable assemblies, and radio system components. Youll steer a specialized engineering team focused on Signal Integrity, guiding end-to-end product lifecycle activitiesfrom concept to high-volume manufacturing qualificationthrough rigorous design, simulation, and testing. This is more than managementit's strategic direction in a fast-evolving tech space where innovation and precision meet performance. Click to Apply - (https://forms.gle/fqb29wUvjNuV82C57) Responsibilities Strategic Leadership: Lead a globally distributed team of experienced SI engineers. Align design activities with organizational goals, customer expectations, and technical standards. Create and manage work plans, project schedules, budgets, and resource allocation. Technical Oversight: Define signal integrity performance parameters for innovative products. Guide complex simulations for multiple protocols: PCIe, USB, Ethernet, etc. Oversee connector design reviews using electromagnetic simulation tools and test validation data. Ensure adherence to qualification processes for high-speed connector interfaces and cable assemblies. Innovation & Execution: Integrate market trends and customer needs into technical roadmaps. Advocate a data-driven design culture through structured simulation reviews and continuous improvement. Lead advanced packaging and PCB layout exploration to support emerging high-speed protocols. Team Development: Build a cohesive, skilled team through talent assessments, structured onboarding, and continuous upskilling. Foster collaboration across geographies and functional disciplines (mechanical, process, materials, product). Provide clear coaching, feedback, and career development plans. Balance workloads and promote wellbeing through flexible, effective leadership. Key Technologies & Tools Signal Integrity Tools: Agilent ADS, Ansys HFSS, CST CAD Platforms: SpaceClaim, AutoCAD, Creo PCB Design: Altium, layout/fabrication validation Test Equipment: VNA, TDR, BERT Data Analysis: Statistical interpretation, tolerance modeling Simulation Interpretation: Channel modeling, S-parameter validation Ideal Candidate Profile 10+ years in electrical or RF design with progressive experience 3+ years of people management and cross-functional leadership Strong grasp of physical layer system architecture and packaging interfaces Skilled communicator able to present to technical and executive audiences Experienced in high-volume manufacturing qualification and risk analysis Proven success building high-performance teams with global collaboration

Role & responsibilities Test bench development and debug UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based testing. Coverage analysis (code, functional, assertion) Verification plan reviews, Verification reviews Back-annotated netlist simulation execution and debug Debug failing cases & Coverage improvements.

Looking for PCB layout design Engineers with the following requirements: Hands-on experience in complex, high-density, high-speed PCBs, Analog, Digital, RF, mixed-signal PCB layout design. Hands-on experience with High-speed interfaces like DDR3,DDR4, LPDDR, , PROCESSORS, FPGA, PCIE, USB, SATA, MIL-1553, ADC, DAC, ETHERNET, NAND & NOR FLASH, SD, RS-422, BLUETOOTH 4.0, WIFI, GPS, GSM etc. Hands on Complex layout HDI designs with multiple BGAs and Multiple Fine pitch BGA (0.8mm and 0.5mm) of high pin count (2084 pins). Library creation as per IPC 7351 standard. Electrical Constrains setup for high-speed modules to match its requirement (Length match, impedance, delay tuning requirements) Experience in Power supply layout design types: AC to DC, DC to DC converters and SMPS. Creation of file type conversions from PCB to DXF, IDF, Step file Power supply layout designs & its critical requirements to meet stringent isolations. Gerber validation and generations of final deliverables for DFM. Working experience on Gerber viewers using Cam350, ODB++ viewer. Collaborating with multiple functional teams like design, SI/PI, mechanical, DFM, DFA etc. in a product development environment knowledge on Power dc, Thermal design, simulation and analysis knowledge of OrCAD schematic Design Tool Collaboration with cross functional teams: Software, Electrical, Mechanical and PCB CAD teams Hands-on experience with Cadence Allegro/Altium EDA/PADS tools is essential. Educational Qualification: B Tech/M. tech/BE/ME, Diploma Location: Hyderabad Shift: General Exp.: 4-6 Years Work Week: Monday to Friday

Must have experience in working with MNC clients Must be good at Honouring Committed Schedules, Quality delivery, Clarity in Communication Familiarity with Serdes components like serializer or de-serializer circuits Strong fundamentals and knowledge of AMS design flow Must have familiarity with layout issues, working with layout team to fix them Must be good at preparing the Review PPT, run through the review meeting and closing all action items Must ensure the design meets PPA goals Good at debugging to ensure meeting all performance simulation issues Must be able to pass QA checks as demanded by the client Must be able to generate all relevant design views using sign-off tools Qualification BE/BTech from any reputed University Masters Preferred Experience Between 3 to 10 years Hands on with any of the spice simulators (Hspice/ Spectre)

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

Looking for PCB layout design Engineer with the following requirements: Hands-on experience in complex, high-density, high-speed PCBs, Analog, Digital, RF, mixed-signal PCB layout design. Exposure with complex 2U, 3U server form factor-based PCB designs. Hands-on experience with High-speed interfaces like DDR3,DDR4/5, LPDDR, , PROCESSORS, FPGA, PCIE, USB, SATA, MIL-1553, ADC, DAC, ETHERNET, NAND & NOR FLASH, SD, RS-422, BLUETOOTH 4.0, WIFI, GPS, GSM etc. Hands on Complex layout HDI designs with multiple BGAs and Multiple Fine pitch BGA (0.8mm and 0.5mm) of high pin count (2084 pins). Library creation as per IPC 7351 standard. Electrical Constraints setup for high-speed modules to match its requirement (Length match, impedance, delay tuning requirements) Experience in Power supply layout design types: AC to DC, DC to DC converters and SMPS. Creation of file type conversions from PCB to DXF, IDF, Step file collaboration with Mechanical Engineer. Power supply layout designs & its critical requirements to meet stringent isolations. Gerber validation and generations of final deliverables for DFM. Working experience on Gerber viewers using Cam350, ODB++ viewer. Collaborating with multiple functional teams like design, SI/PI, mechanical, DFM, DFA etc. in a product development environment knowledge on Power dc, Thermal design, simulation and analysis knowledge of OrCAD schematic Design Tool Collaboration with cross functional teams: Software, Electrical, Mechanical and PCB CAD teams Hands-on experience with Cadence Allegro/Altium EDA/PADS tools is essential. Education Requirements: B. Tech/B.E./M. Tech./M.E. Shift: 9:30 AM to 6:30 PM Work Mode: Office (Monday to Friday)

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world Our mission is to build great products that accelerate next-generation computing experiences the building blocks for the data center, artificial intelligence, PCs, gaming and embedded Underpinning our mission is the AMD culture We push the limits of innovation to solve the worlds most important challenges We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives AMD together we advance_ Lead SOC Verification Engineer The Role You have a passion for modern, complex processor architecture, digital design, and verification in general You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems The Person A successful candidate will work with senior silicon design engineers The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills Key Responsiblities Fair understanding on protocols : AXI3/DDR/ACE/CHI is a must Prior work experience on High-Speed Serials PCIe/CXL/USB/SATA/GT/SerDes IP's is preferred Preferred Experience Minimum 12+ year of industry experience in IP/SOC level design verification Have worked upon atleast one full cycle of SoC Verification flow Strong SV/UVM, UVC, Scoreboards, Functional coverage, SV assertions, C/C++ expertise Able to create APIs for SOC level test bench stimulus Strong debug expertise Must have good communication skills and ability to work in a team environment Experience in data path verification protocol like PCIe/CXL/AXI/SATA at SoC Level Experience in driving task independently and complete with excellent quality Academic Credentials Bachelors or Masters degree in computer engineering/Electrical Engineering Benefits offered are described: AMD benefits at a glance AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law We encourage applications from all qualified candidates and will accommodate applicantsneeds under the respective laws throughout all stages of the recruitment and selection process

Min 10 yrs of R&D experience in FPGA development (Altera, Xilinx) Experience of RTL languages - VHDL or Verilog Xilinx FPGA Tools Design Flow - Vivado, Chipscope, Quartus. EDA Functional Simulation tools – Synopsys or Mentor or Cadence.

5+ exp in verification at IP/sub-system level. Well versed in (Digital design, SV, UVM). Experience in DDR, PHY protocols. Responsibilities: Develop and execute comprehensive verification plans and testbenches. Write high-quality, efficient, and reusable verification components. Create and maintain detailed verification documentation. Debug complex verification issues and propose solutions. Collaborate with design engineers to ensure design quality and performance. Stay up-to-date with the latest verification methodologies and tools.

Key responsibilities: Experienced in all the phases of Hardware Development Life Cycle including requirements analysis, component selection, design, development, testing, and documentation. Vendor coordination for component selection, PCB Fab, and Assembly house. Involved in supporting proto build, pilot build, and mass production. Co-ordinating with Software/firmware team for the board bring-up and successful system integration. Should be capable of preparing the proposal based on customer requirements Should be capable of executing the project from requirement gathering to final product/service deliverables Should be capable of managing 3 to 4 sub-ordinates Responsible for team collaboration, reduce attrition and skills development Should be capable of interacting with other teams and get the work on time Technical Skills: Mandatory requirement on having experience in Microprocessor/Microcontroller based embedded hardware (digital) board design. On-Board Power distribution/management design with DC-DC Switching regulators & LDO. Knowledge in Analog and mixed-signal board design. Development of product in coordinating with PCB and mechanical CAD and review/guidance to Layout Designers for Component logical/mechanical placement, Power Plane creation, and PCB Designing. Mandatory Tools Skills: Cadence OrCAD for schematics, Allegro/Altium experience for PCB board Design review Knowledge of interfaces like MIPI CSI, SD Interface, Ethernet, RGMII, USB, LVDS, GMSL, SPI, UART, I2C etc.., Physical layer level understanding and debugging skill. Preferred skills(Added advantage): Knowledge in PCB layer stack-up, signal integrity, thermal simulation, environmental tests, FCC and EMI/EMC compliance testing

Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based onImplementation means trying, testing, and improving outcomes until a final solution emerges . Knowledge means exchange discussions with colleagues from all over the world. Join our team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation. We make real what matters. This is your role. Questa verification IPs help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will get along with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We dont need superheroes, just super minds. You're an Electronics Engineer ( B.Tech / M.Tech ) or related field from a reputed institute You've got phenomenal knowledge of verification engineering and have between 2 - 8 years of working experience as well. You've sound knowhow of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe , Flash, DIMM etc. You are a great teammate, resilient and sincere, Enjoy learning new things and build knowledge base in new area. Weve got quite a lot to offer. How about you This role is based in" Noida " but " youll get the chance to work with teams impacting entire cities, countries- and the shape of things to come. The pace of innovation in electronics is constantly accelerating. To enable our customers to deliver life-changing innovations to the world faster and to become market leaders, we are committed to delivering the worlds most comprehensive portfolio of electronic design automation (EDA) software, hardware, and services. We, at Siemens EDA enable companies to develop better electronic products faster and more efficiently. Our innovative products and solutions help engineers conquer design challenges in the increasingly sophisticated worlds of board and chip design We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate

Job Role Overview: The ideal candidate for this role will be an innovative self-starter. You will be a DDR/LPDDR expert with experience in making architectural trade-offs to optimize DDR/LPDDR performance & power for a variety of use cases. You will collaborate with internal and external development engineers (architecture, hardware, validation, software services). You will be a member of a team analysing the product-level system power & performance for DDR/LPDDR. You will contribute to development, support device characterization, and benchmarking efforts. Job Description : Extensive experience in DDR/LPDDR systems Experience in development, preferably for DDR/LPDDR memory controller. In-depth knowledge and extensive experience with JEDEC specifications for DDR/LPDDR. In-depth knowledge and extensive experience in embedded domain. Requirements: B. Tech in Computer Science, Electrical Engineering. 8+ years of experience in a relevant domain. Strong analytical & abstract thinking ability, along with technical communication skills. Able to work independently and perform in a fast-paced environment. Ability to troubleshoot and debug complex issues. Prior experience in working with Agile/Scrum.

Reporting to: Lead Engineer. Job Description. Create Schematics using Computer-Aided Design Altium/ Eagle platform tools.. Create PCB Circuit layouts and documentation from schematics using Altium/ Eagle tools considering Layer Stack up, Multilayer Board, EMI/EMC checks, High Speed Design etc.. Designed up to 8 layers. Worked in Mixed signal, powerboard, RF boards of placement and routing with guidelines.. Important High-Speed Interfaces: Processor, DDR3, USB3, MIPI CSI-DSI, EMMC, SDIO and wireless interface antenna Layout Design. Worked on protecting high frequency signals and clock signals from interfacing and noise by providing ground guarding. Knowledge on Layer Stack-up for Impedance control boards, Power boards and High Speed SOC Board. Knowledge on using blind and buried vias.. Process PCB , Flex and rigid-flex Circuit layouts for pattern generation, documentation, and Computer-Aided Manufacturing (CAM) files for fabrication and assembly. Work closely with Product Design Engineers, Mechanical Engineers, and Designers to produce the optimal PCB and for power supplies distribution layout, and other product circuits. Produce and maintain all documentation and engineering drawings for PCB Circuit designs. Creating PCB footprints SMD & Through hole as per IPC standards and component library Development.. Design Rule check and net list analysis to generate error free net list. Incorporate Engineering Change Orders (ECOs) to PCB Circuit designs.. Uses tools to calculate dimensions and tolerances to assure function, fit, and manufacturability of components and assemblies, and performs component research to recommend design alternatives, and contributes to technical designs and documentation.. Maintain the record of PCB design and its revision.. May perform other duties as assigned. Provide support to collaborate with Electronics Manufacturing Service vendors. Familiar with communication protocols such as USB, I2C, SPI, UART, I2S and implementation practices of the same on PCB Layout. Diverse experience in multicore microcontroller/ microprocessor based circuit design and bring-up. Ideally from ST/TI/NXP/Embedded OS based SOC and sensor interface on PCBA level.. Qualification. Degree/Diploma holders in Electronics and Telecommunication. 5+ years of experience in PCB designing using Altium tool.. Hands on experience in Alitum Library Management. Good understanding of Electronics part and their packages. Good communication skill. Show more Show less

As a Hardware Engineer, you will play a key role in the design, debugging, and validation of cutting-edge hardware solutions for Nokias Optical Networking products. Your work will directly contribute to the development of high-performance systems that power global communications infrastructure. In an increasingly connected world, the pandemic has highlighted just how essential telecom networks are to keeping society running.The Network Infrastructuregroup is at the heart of a revolution to connectivity, pushing the boundaries to deliver more and faster network capacity to people worldwide through our ambition, innovation, and technical expertise Join Optical Networks division, where innovation meets scale in the AI-driven data center era. With the recent acquisition of Infinera, weve united two industry leaders to create an optical networking powerhousecombining cutting-edge technology with proven leadership to redefine the future of connectivity. Infinera is now part of the Nokia Corporation and its subsidiaries. When you apply, the information you share will be handled with care and used only for recruitment purposes within the group. Youll have the freedom to explore new ideas and grow your technical and professional skills. Experience in designing boards with Microprocessors, Microcontrollers, FPGAs and CPLDs Working knowledge of high-speed interfaces like PAM4, PCIe, DRR4, SATA, USB, SGMII etc. Knowledge of various memories (DDR, NAND, NOR etc) Experience in designing boards in telecom domain Knowledge of SI and PI concepts, Timing concepts Experience with Concept HDL schematic entry Hands-on experience with lab equipment like high speed oscilloscope, signal source analyzer, spectrum analyzer, logic analyzer, bode analyzer etc. Good communication and documentation skills Conduct feasibility analysis during the architecture phase. Design hardware that meets requirements. Perform component selection, schematic entry, BoM release, support layout engineers, and support the manufacturing team during prototyping. Conduct board bring-up, functional testing, and support cross-functional teams during system testing and debugging issues. Debug field issues of released products.

"We're Hiring For Lead Hardware Engineer role at Chennai Location" Position: Lead Hardware Engineer Experience: 15+ Years Location: Chennai Key Responsibilities: Independently lead electrical hardware design tasks for automotive systems. Review and analyze customer specifications and translate them into design requirements. Design and develop automotive electronics including: Microcontrollers, SoCs, high-speed memory interfaces LVDS and FPD-Link III circuitry High-speed digital and analog circuits Audio, camera, and video signal processing Linear and switching power supplies Perform worst-case analysis and circuit simulations to ensure compliance with specifications. Conduct and support formal design reviews and customer presentations. Create and maintain schematics, BOMs, and assembly drawings under change control processes. Develop and maintain DFMEA documentation for electrical systems. Collaborate with ECAD engineers for PCB layout and provide design support. Support prototype hardware builds and validate product performance. Develop test plans and perform electrical verification testing. Support EMC compliance and validation testing processes. Use structured problem-solving techniques to resolve design and testing issues. Operate lab instruments such as oscilloscopes, power supplies, function generators, and multimeters for design verification and debugging. More information +91 73597 10155 | rushit@tekpillar.com

"We're Hiring For Lead Hardware Engineer role at Chennai Location" Position: Lead Hardware Engineer Experience: 5+ Years Location: Chennai Key Responsibilities: Independently lead electrical hardware design tasks for automotive systems. Review and analyze customer specifications and translate them into design requirements. Design and develop automotive electronics including: Microcontrollers, SoCs, high-speed memory interfaces LVDS and FPD-Link III circuitry High-speed digital and analog circuits Audio, camera, and video signal processing Linear and switching power supplies Perform worst-case analysis and circuit simulations to ensure compliance with specifications. Conduct and support formal design reviews and customer presentations. Create and maintain schematics, BOMs, and assembly drawings under change control processes. Develop and maintain DFMEA documentation for electrical systems. Collaborate with ECAD engineers for PCB layout and provide design support. Support prototype hardware builds and validate product performance. Develop test plans and perform electrical verification testing. Support EMC compliance and validation testing processes. Use structured problem-solving techniques to resolve design and testing issues. Operate lab instruments such as oscilloscopes, power supplies, function generators, and multimeters for design verification and debugging. More information +91 73597 10155 | rushit@tekpillar.com

Role Purpose The purpose of this role is to lead the VLSI development and design of the system by defining the various functionalities, architecture, layout and implementation for a client 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 3. Team Management a. Resourcing i. Forecast talent requirements as per the current and future business needs ii. Hire adequate and right resources for the team iii. Train direct reportees to make right recruitment and selection decisions b. Talent Management i. Ensure 100% compliance to Wipros standards of adequate onboarding and training for team members to enhance capability & effectiveness ii. Build an internal talent pool of HiPos and ensure their career progression within the organization iii. Promote diversity in leadership positions c. Performance Management i. Set goals for direct reportees, conduct timely performance reviews and appraisals, and give constructive feedback to direct reports. ii. Incase of performance issues, take necessary action with zero tolerance for will based performance issues iii. Ensure that organizational programs like Performance Nxt are well understood and that the team is taking the opportunities presented by such programs to their and their levels below d. Employee Satisfaction and Engagement i. Lead and drive engagement initiatives for the team ii. Track team satisfaction scores and identify initiatives to build engagement within the team iii. Proactively challenge the team with larger and enriching projects/ initiatives for the organization or team iv. Exercise employee recognition and appreciation Deliver No. Performance Parameter Measure 1. Verification Timeliness, Quality and coverage of verification, Compliance to UVM standards, Customer responsiveness 2. Project documentation and MIS 100% on time MIS & report generation Complete Project documentation (including scripts and test cases) 3. Team % trained on new skills, Team attrition %, Employee satisfaction score (ESAT) Mandatory Skills: ASIC Design. Experience5-8 Years.

Long Description 1. ASIC RTL Engineer : RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory PCIe/DDR/Ethernet - Any One I2C,UART/SPI - Any One Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One scripting languages like Make flow, Perl ,shell, python - Any One LocationBangalore / Hyderabad / Kochi Experience - 7+ - Lead/Architect 2. Emulation Lead JD - Emulation Lead (Zebu/ HAPS /Veloce/Palladium and Module Build (End to End) Location - Bangalore / Hyderabad Experience - 7+ - Lead/Architect 3. Lead Design Verification Engineer : 7+ years of hands-on DV experience in SystemVerilog/UVM. Must be able to own and drive the verification of a block / subsystem or a SOC. Should have a track record of leading a team of engineers. Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. Experience in Tesplan and Testbench development, Execution of test plan using high quality constrained random UVM tests to hit coverage goals on time. Should be good with debugging and exposed to all aspects of verification flow including Gatesims Must have extensive experience in verification of one or more of the following: PCI Express or UCIe, CXL or NVMe AXI, ACE or CHI Ethernet, RoCE or RDMA DDR or LPDDR or HBM ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages Power Aware Simulations using UPF Experience in using one or more of EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, Jasper. Experience in using one or more of revision control systems such asGit, Perforce, Clearcase. Experience in SVA and formal verification is desirable (not a must) Script development using Python, Perl or TCL is desirable (not a must) Location - Bangalore, Hyderabad, Kochi, Pune, Ahmedabad, Pune Experience - 7+ YoE Long Description 4. Analog Circuit Design : Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Experience - 7+ Yrs + Lead/Architect Location - Bangalore 5. DFT - ATPG, MBIST Location - Bangalore, Kochi, Pune, Hyderabad Experience - 7 years + DFT Lead Mandatory Skills: VLSI HVL Verification. Experience5-8 Years.

Roles and Responsibilities Design verification using UVM (Universal Verification Methodology) for IP/SoC level verification. Develop test benches from scratch, including creating drivers, monitors, and predictors. Utilize System Verilog to write verification code and debug issues. Collaborate with cross-functional teams to identify requirements and develop test plans. Participate in peer reviews to ensure high-quality deliverables. Desired Candidate Profile 4-10 years of experience in SOC/IP Verification with expertise in DV on Cpu, DDR, Ethernet, PCIe protocols. Bachelor's degree (B.Tech/B.E.). Master's degree preferred but not mandatory (M.Tech). Strong understanding of GLS (Global Logic Synthesis) concepts.

Roles and Responsibilities Design verification using UVM (Universal Verification Methodology) for PCIe, DDR, Ethernet interfaces on SOCs. Develop test benches in System Verilog for verifying complex digital designs. Collaborate with cross-functional teams to identify requirements and develop test plans. Utilize GLS (Golden Labs Simulation) tools for simulation setup and debugging. Participate in peer reviews to ensure high-quality deliverables. Must have good debugging skills. Experience in any of the slow speed peripherals like I2C, SPI, UART is a plus. Desired Candidate Profile 5 years of experience in SV/UVM Lead role with expertise in design verification using UVM methodology. Bachelor's degree (B.Tech/B.E.). Master's degree preferred but not mandatory (M.Tech). Strong understanding of SystemVerilog programming language and its application in DV testing.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP designs ( PCIe, USB, MIPI, CXL, C2C, D2D, DDR, PLL, DAC, ADC, Sensors, etc.) for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle, from system-level concept to tape out and post-silicon support. Responsibilities Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team. Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Analog/mixed signal simulation, Low power verification, Formal verification and Gate level simulation to ensure high design quality. Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure. Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful PHY level verification, integration into subsystem and SoC, and post-silicon validation. Minimum Qualifications Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. 12+ years ASIC design verification, or related work experience. Knowledge of a HVL methodology like SystemVerilog/UVM. Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others. Preferred Qualifications Experience with Low power design verification, Formal verification and Gate level simulation. Knowledge of standard protocols such as PCIe, USB, MIPI, LPDDR, etc., Experience in scripting languages (Python, or Perl). Experience with mixed-signal IP design verification, such as USB, PCIe, CXL, C2C, D2D, MIPI, UFS, DDR, PLL, Data Convertors (DAC, ADC), or sensors.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: 10+ years of experience in the embedded domain to design, develop and support software solutions on multi-core ARM (V7A or V8A)/CPUs, Strong C/C++ programming skills. Embedded Platforms experience including low-level firmware, kernel (Linux or QNX), Hypervisor/Virtualization and user-space components. Design and development of software for heterogeneous compute platforms consisting of ARMs, GPUs, DSPs, and specialized hardware accelerators in an embedded SoC systems with J-TAG or ICE debuggers. Experience in real-time SW development for embedded products. Hands-on experience using JTAG to debug real-time problems Hands-on experience using different version control systems like perforce, GIT Expertise in Development of PCI RC/EP Device Driver. Expertise in writing kernel space device drivers in areas of MMU, Power(clocks/thermal). Solid understanding of Linux/QNX boot flow on embedded systems. Solid understanding of computer system architecture (core, cache, memory models, bus architecture, etc.). Experience in Board Bring-up, Device drivers, peripheral buses (SPI, I2C, USB), Memory controller DDR, eMMC, UFS and Performance. Solid understanding of different debug methods offered by Linux Kernel/QNX. Motivated self-starter with excellent verbal and written communication skills, demonstrated ability to work with engineers/partners/customers across different geographies. Hands-on technical lead who is not hesitant to dig into the details where needed to get first-hand knowledge of the issues and play an active and personal role in steering team success Collaborate with internal teams and external partners on analysis and debugging. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.

Handson experience of baremetal FW development in Pre Si w/ UVM TB, debugging FW using Verdi/Sim Vision along with RTL,basic signal tracing in Verilog, High-Speed Serial I/F for 2yrs : UCIe, PCIe, CXL, HBM, Qlink (Qualcomm), DigRF (MIPI)