4 Verilog Coding Jobs

You will be responsible for DFX Verification as a DFX Engineer at Eximietas. With 4-10 years of experience, you should have a good background in SoC RTL verification and debug, GLS simulations and debug, Verilog coding, and a solid understanding of JTAG and verification in Test Mode. It would be beneficial to have experience in pattern generation and Silicon debug. The role does not require MBIST/SCAN related experience. The location for this position is Visakhapatnam. If you meet the requirements and are interested in this opportunity, please share your updated resume with us at maruthiprasad.e@eximietas.design.,

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

You will be responsible for RTL ASIC front end design with Microarchitecture and Verilog coding. Your tasks will include MAS development, RTL coding, development of modules, and feature additions. You should have experience in working with medium complexity protocols and be well-versed in slow-speed protocols like I2C, SPI, and UART. Familiarity with AMBA bus protocols (APB, AHB, AXI) is required. Additionally, you should have experience in Quality check flows, including lint and CDC. For candidates with 8+ years of experience, you are expected to be very strong in RTL coding. Your role will involve microarchitecture development, owning and delivering a subsystem or top level in a SoC project, expertise in IP design, subsystem design, SoC integration, and successful leadership of a team to deliver projects on time. If you are interested in this position, please share your updated CV with gayatri.kushe@tessolve.com or connect on 6361542656.,

As a new, exciting, and challenging position, we are looking for a talented person that can show a great level of initiative and ability to work in a busy and fast-changing environment. This rewarding role is fundamental to the successful and smooth operation of the engineering teams. You will play a vital role in helping to strengthen and develop forecasting capabilities, based upon improved monitoring capacity andforward-looking project schedules. You will generate test benches and test cases, perform RTL and gate-level SDF-annotated simulations and debug, and may perform mixed-signal (digital + analog) simulations and debug. You will interact with our application engineers and provide guidance to customers. Additionally, you will participate in the generation of data books, application notes, and white papers. What You ll Be Doing: Generate test benches and test cases. Perform RTL and gate-level SDF-annotated simulations and debug. May perform mixed-signal (digital + analog) simulations and debug. Interact with our application engineers and provide guidance to customers. Participate in the generation of data books, application notes, and white papers. Perform physical verification and design rule checks to ensure design integrity andmanufacturability. Understand tools like VC Spyglass, Verdi, & views like SDF, Liberty, etc., and other frontend views. Write RTL Code, with solid Verilog, PERL, and Python skills, and TCL is a good addition. Understand static timing analysis and synthesis, DFT/ATPG skills would be a plus. Knowledge of any high-speed communication protocol is not mandatory but an asset. Previous knowledge in customer support and/or silicon bring-up is a plus. The Impact You Will Have: Strengthen and develop forecasting capabilities based on improved monitoring capacity. Ensure high-quality and reliable silicon lifecycle monitoring solutions. Enhance quality assurance methodology by adding more quality checks/gatings. Support internal tools development and automation to improve productivity across ASIC design cycles. Work with design engineers on newtools/technology and new features evaluation and adoption. Contribute to the successful and smooth operation of the engineering teams. What You ll Need: Bachelor s or master s degree in electrical engineering or a related field. 3 to 7+ years of experience in A&MS frontend and backend views & collaterals development flows. Proficiency inindustry-standard EDA tools, such as Cadence Virtuoso or Synopsys Custom Compiler. Exceptional knowledge of layout design methods, techniques, andmethodologies. Experience with physical verification tools, such as Calibre or Assura. Understanding of semiconductor process technologies and their impact on layout design. Who You Are: Excellentproblem-solving and systematic skills. Ability to work effectively in a team-oriented environment. Familiarity with Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV). Good communication and interpersonal skills.