UVM and GenAI Engineer - Automatic Testbench Generation

You will be joining our team as an experienced UVM and GenAI Engineer, focusing on developing innovative solutions using Generative AI to automatically generate testbenches for complex digital designs. Your responsibilities will include collaborating with design and verification teams, implementing Generative AI algorithms, designing UVM-based testbenches, and integrating AI-generated testbenches into the verification flow. You will also be required to stay updated with the latest developments in UVM, GenAI, and digital design verification, participate in code reviews, and contribute to enhancing the team's verification methodologies. To qualify for this role, you should hold a Bachelor's/Master's degree in Computer Science, Electrical Engineering, or a related field, along with at least 6 years of experience in digital design verification with a focus on UVM-based testbenches. Proficiency in UVM, SystemVerilog, digital design principles, AI/ML frameworks, programming languages like Python, C++, and systemVerilog, as well as experience with version control systems like Git, are essential. Strong problem-solving skills and the ability to work both independently and collaboratively are also key requirements. It would be advantageous if you have experience with Generative AI algorithms, digital design languages such as VHDL or Verilog, cloud-based AI platforms like AWS SageMaker or Google Cloud AI Platform, and Agile development methodologies. In return, we offer a competitive salary and benefits package, the opportunity to work on cutting-edge AI technology and digital design verification, a collaborative work environment, professional development opportunities, and flexible working hours with remote work options. If you are a motivated individual with a passion for UVM, GenAI, and digital design verification, we encourage you to submit your resume and a cover letter detailing why you are the perfect fit for this role.,