Senior Methodology Engineer Low Power Structural Checks Arm

5.0 - 9.0 years

0 Lacs

karnataka

On-site

As a member of the methodology team in the Design Engineering category based in Bengaluru, India, your primary responsibility will be to lead the development, enhancement, and deployment of low-power structural check methodologies for multiple SoC and IP projects. Your role will involve creating automated flows to ensure UPF/CPF consistency, power domain integrity, and structural rule validation at both RTL and netlist levels. Collaboration with design, verification, and EDA partners will be essential to establish robust, scalable, and high-coverage power-aware design signoff strategies across different technology nodes and product segments. Your key responsibilities will include developing and maintaining low-power structural check methodologies, building automated flows using tools like Synopsys VC LP, SpyGlass-LP, and Conformal LP, ensuring power intent consistency, integrating structural checks into signoff regressions, and collaborating with vendors and internal teams to enhance tools and drive global adoption. You will also be involved in audits, quality reviews, and milestone checks to maintain the quality of the methodologies. To excel in this role, you should possess at least 5 years of experience in low-power structural methodologies and UPF/CPF-based flows. A deep understanding of power intent specs, domain partitioning, isolation, and retention is crucial, along with hands-on experience with tools like VC LP, SpyGlass-LP, or Cadence CLP. Proficiency in scripting (Python, Perl, TCL) for flow automation, experience with large SoC/IP designs, and strong communication and documentation skills are also required. Nice to have skills and experience include familiarity with formal verification or functional simulation for power-aware designs, knowledge of complex power analysis, exposure to hierarchical low-power signoff strategies, and involvement in industry working groups or technical conferences. Additionally, experience with power-aware DFT, scan strategies, and low-power aware synthesis flows will be advantageous. At Arm, we value behaviors such as partnership, dedication, collaboration, communication, originality, resourcefulness, team and personal development, impact, and influence. If you require any accommodations during the recruitment process, please reach out to accommodations@arm.com. We believe in equal opportunities and offer a hybrid working environment that promotes flexibility and personal wellbeing. Join us in shaping extraordinary teams and making a difference in the world of technology.,

Posted 3 days ago

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