Lead / Principal Analog Design Engineer Cadence

5.0 - 15.0 years

0 Lacs

pune, maharashtra

On-site

You will be responsible for designing and leading the development of high-speed IP such as GDDR7, DDR5, and LPDDR6. As a strong individual contributor in the analog domain, you will actively participate in all aspects of development including analog design, layout, digital design, documentation, and silicon validation. Your role will also involve engaging in customer-facing discussions to address their requirements and concerns. To qualify for this position, you should hold a B.Tech / BE / ME / Mtech degree with at least 5 to 15+ years of experience. It is essential to have hands-on design experience and leadership skills in GDDR/DDR/LPDDR IPs. A successful candidate must have been involved in the entire cycle of analog IP creation, from specification to silicon debugging and characterization. Good communication skills and the ability to work effectively in a team are crucial for this role. Moreover, expertise in areas such as PLL, high-speed circuits like TX, RX, clocking circuits, etc., is mandatory. Experience with other common IP blocks like BGR, LDO, POC, temperature sensor, etc., would be considered advantageous.,

Posted 4 days ago

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