4 Sram Design Jobs

Role and Responsibilities SRAM design group in Bangalore develops various types of SRAMs, Registerfiles and ROMs in advanced technology nodes like 4nm, 2nm and beyond. The team is responsible for delivering highly competitive memories for the SAMSUNG Foundry customers. Provides a unique opportunity to the individuals who are willing to innovate and solve the most challenging problems in the field of circuit design. Samsung Foundry being a pioneer in new device technology, it creates ample opportunities for the circuit designer to innovate and design highly competitive IPs. Design highly competitive circuits to meet performance/power specifications requested by customers. Guide and lead a group of engineers to deliver the SRAM IP in the given timelines. Analyse circuits and identify potential robustness gaps and find solutions to improve robustness of the design. Own the responsibility from SPEC to GDS and DK delivery. Review circuits, robustness reports and identify potential robustness issues. Review layouts and suggest improvement areas to achieve competitive PPA. Understanding of SRAM PPA trade-offs and identify right techniques to meet SPEC. Must be able to communicate effectively across different teams. Skills and Qualifications Master/Bachelor in electronics Working experience (10+ years) preferably in Memory design Understanding of RC network and FinFET fundamentals are necessary Custom or Compiler SRAM/ROM development experience Fundamentals of process variability and its effect on memory design Thorough understanding of SRAM bit cell and its characteristics (Read current, Standby current, data retention, SNM) Strong understanding of circuit design fundamentals Critical path modeling concept, various types of models (RC, C, Pi, ladder) Good knowledge of semiconductor physics, like knowledge of FinFET function, parasitics etc Analysing layout and understanding of LLE effects Bachelor's / Master degree in Computer Science, Electrical/Electronics Engineering, Engineering and 10+ years of experience in circuit design

What You'll Be Doing: Develop CMOS embedded memories such as SP SRAM, DP SRAM, Register File, and ROM. Design architecture and circuit implementation, focusing on ultra high speed, ultra low power, or high density designs. Perform schematic entry, circuit simulation, layout planning, layout supervision, design verification, and validation. Interface with CAD and Frontend engineers for memory compiler automation, EDA model generation, and full verification flow. Perform bit cell development and verification, and drive physical layout design and verification. Provide support and/or perform other duties as assigned and required. The Impact You Will Have: Contribute to the development of high-performance silicon chips and software content. Enhance the efficiency and performance of our CMOS memory designs. Drive innovation in ultra high speed, ultra low power, and high density memory designs. Ensure the highest quality in bit cell development and physical layout design. Collaborate effectively with CAD and Frontend engineers to streamline automation and verification processes. Support the continuous improvement and advancement of our memory design technology. What You'll Need: Bachelor's or Master's degree in Electrical Engineering, Telecommunication, or related fields. Proficiency in CMOS memory design, circuit simulation, memory layout designs, layout parasitic extraction, and layout verification tools and debugging techniques. Programming capability in C-Shell and Perl; knowledge of C++ or Java script is a plus. Strong analytical and problem-solving skills with attention to detail. Experience in developing documents, reports, or presentations for a range of tasks. Who You Are: Self-motivated, self-directed, detail-oriented, and well-organized. Possess excellent analytical, problem-solving, and negotiation skills. Capable of leading and mentoring trainees and junior engineers, as well as managing projects. Strong command of English, both verbal and written. Exhibit strong interpersonal communication and teamwork skills. Professional, critical/logical thinker, and focused on future goals. Highly committed to continuous learning and professional development.

What You'll Be Doing: Designing, developing, and troubleshooting embedded memory compilers. Applying skills in memory compilers, focusing on transistor-level circuit design. Understanding various memory design aspects such as read/write margins and timing races to find effective solutions. Interacting with the layout team to address and resolve issues from both design and layout standpoints. Working independently on tasks, ensuring ownership and collaboration to achieve optimal results. Engaging frequently with senior personnel to leverage expertise and enhance project outcomes. The Impact You Will Have: Enhancing the performance and reliability of embedded memory compilers. Driving innovation in memory design, contributing to the development of high-performance silicon chips. Collaborating with cross-functional teams to optimize design and layout processes. Ensuring timely delivery of robust and efficient memory solutions. Contributing to the continuous improvement of design methodologies and practices. Supporting the advancement of Synopsys technology leadership in the semiconductor industry. What You'll Need: 2-5 years of experience in Embedded SRAM compilers. Strong understanding of CMOS digital circuits. Knowledge of FinFET technology (preferred). Proficiency in transistor-level circuit design. Ability to analyze and resolve design and layout issues effectively. Who You Are: Innovative and detail-oriented. Collaborative team player. Effective communicator with strong interpersonal skills. Problem-solver with a proactive approach. Self-motivated and able to work independently.

Introduction As a Hardware at , youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in todays market. Your role and responsibilities -Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise -12+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.