5 Simd Jobs

Key Skills: Cluster, C++, Java, SIMD, AVX, OpenCV, OpenMP, OpenCL. Roles and Responsibilities: Understand project specifications and performance requirements and drive adherence to project timelines, ensuring program milestones are achieved on schedule. Lead and expand a team of software engineers while ensuring effective collaboration within the team. Manage time and organizational tasks efficiently to meet development objectives. Adapt swiftly to changes within the fast-paced high-performance computing industry. Identify and address bottlenecks in data movement, code execution, and job scheduling. Leverage in-depth knowledge of Linux systems and internals to support HPC infrastructure. Apply proficiency in Shell and Python scripting to support testing and automation. Ensure optimized performance of parallel and distributed computing applications. Experience Requirement: 3 to 5 years of validated experience in HPC or a related engineering domain. Strong Object-Oriented programming skills in Java and/or C++. Proven proficiency in parallel programming and distributed computing techniques. Strong understanding of HPC hardware including servers, GPUs, networking, storage, BIOS, and BMC. Experience with performance profilers such as Intel vTune, Nvidia Nsight Compute, AMD uProf, and perf is preferred. Familiarity with libraries such as SIMD, AVX, IPP, MKL, OpenCV, OpenMP, OpenCL, MPI, and CUDA is advantageous. Experience with observability tools for distributed systems like Prometheus and Grafana is a plus. Demonstrated ability to work effectively in a team, manage tasks efficiently, and adapt to evolving priorities. Education: B.Tech M.Tech (Dual), B.E., B.Tech.

What We Expect 4+ years of experience in C++ development, specializing in high-performance, low-latency systems. Deep expertise in modern C++ (C++14/17/20), multithreading, and concurrency. Strong Qt development experience for building real-time, high-performance trading UIs. Experience building ultra-fast order execution engines, market data feeds, and real-time risk management tools. Strong understanding of networking protocols (TCP/IP, UDP, FIX) and inter process communication (IPC, shared memory, message queues). Hands-on experience with latency optimization, performance tuning, and profiling tools (perf, Val grind, gprof, etc.). Proficiency in memory management, lock-free programming, and CPU cache optimization. A deep understanding of exchange connectivity, order matching engines, and algorithmic trading systems. A hacker mentality-you love solving problems that seem impossible. What You Will Do Architect, develop, and optimize ultra-low-latency C++ trading applications that handle millions of transactions per second. Build high-performance market data processing solutions with microsecond-level latencies. Develop real-time, intuitive, and high-speed trading interfaces using Qt. Work on exchange connectivity, FIX protocol integrations, and risk management systems. Profile and optimize code to achieve maximum throughput and minimal latency. Solve some of the hardest engineering problems in fintech alongside an elite team. Experiment with new technologies to stay ahead of the competition. Own your work end-to-end-from concept to deployment, pushing the limits of what's possible. Must-Have Skills 4+ years of experience in C++ development, specializing in high-performance, low-latency systems. Deep expertise in modern C++ (C++14/17/20), multithreading, and concurrency. Strong Qt development experience for building real-time, high-performance trading UIs. Experience building ultra-fast order execution engines, market data feeds, and real-time risk management tools. Strong understanding of networking protocols (TCP/IP, UDP, FIX) and inter process communication (IPC, shared memory, message queues). Hands-on experience with latency optimization, performance tuning, and profiling tools (perf, Val grind, gprof, etc.). Nice-to-Have Skills Experience in high-frequency trading (HFT), market-making, or ultra-low-latency environments. Knowledge of exchange matching algorithms, order routing strategies, and market microstructure. Contributions to open-source C++ and Qt projects or performance-critical software. Expertise in hardware acceleration (FPGA, SIMD, AVX, GPU computing). Familiarity with cloud-based trading infrastructure and hybrid on-prem/cloud systems.

Staff IP/RTL Design Engineer (AI Accelerator) Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Senior Physical Fri, Mar 28 at 9:39 AM Principal / Staff IP/RTL Design Engineer (AI Accelerator) Multiple positions - Hyderabad Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Principal / Staff IP/RTL Design Engineer (AI Accelerator) Hyderabad Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad/ Bangalore A US based well-funded product-based startup looking for Highly talented Senior Physical Fri, Mar 28 at 9:39 AM Principal / Staff IP/RTL Design Engineer (AI Accelerator) Multiple positions - Hyderabad Well-funded product startup is looking for RTL Design Engineers to contribute to the development of novel high performance AI accelerators from scratch. In this role you will collaborate with cross-functional teams, including architect, software, verification, physical design, systems engineers, to define and implement next generation AI architectures. We are seeking highly experienced individuals who have a passion for innovation and are excited about the opportunity to create world class products from India. The key responsibilities for this role include, but are not limited to: Key Responsibilities Design and implement high-performance TPUs/MPUs and other related AI blocks using RTL. Own IP/block-level RTL from spec to GDS, including design, synthesis, and timing closure. Optimize design for power, performance, and area (PPA). Interface with physical design and DFT (Design for Test) engineers for seamless integration. Drive design reviews, write design documentation, and support post silicon bring-up/debug. Minimum Qualifications B.S./M.S./Ph.D. in ECE/CS from top engineering college with 5-15 years of related experience. Previous experience in either high performance processor design or AI accelerator design is plus. Clear understanding of floating-point arithmetic, vector processing, SIMD, MIMD, VLIW, EPIC concepts. Strong grasp of digital design fundamentals, computer architecture, virtual memory and high-speed data-path design. Proficiency in Verilog/SystemVerilog and simulation tools. Experience with EDA tools (e.g., Synopsys, Cadence) for synthesis, lint, CDC, and timing analysis. What is in it for you? Pure play product work environment Chance to work with a tightly knit group of exceptional engineers who come from the top companies of the Semiconductor world Our pay comprehensively beats "ALL" Semiconductor product players in the Indian market. A meritocracy first work place where each peer is a star A chance to be a part of industry shaping product in entirety (not bits and pieces) from initial stages A chance to work at a startup which already has customers and investor lined up for their product pipeline (We do not have a marketing/sales team, because we do not need them). A chance to learn from industry veterans who have already launched multiple Billion Dollar Semiconductor firms over the last 3 decades. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Senior Software Technical Director / Software Technical Director Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon We are looking for a Software Technical Director with a strong technical foundation in systems software, Linux platforms, or machine learning compiler stacks to lead and grow a high-impact engineering team in Bangalore. You will be responsible for shaping the architecture, contributing to codebases, and managing execution across projects that sit at the intersection of systems programming, AI runtimes, and performance-critical software. Key Responsibilities: Technical Leadership: Lead the design and development of Linux platform software, firmware, or ML compilers and runtimes. Drive architecture decisions across compiler, runtime, or low-level platform components. Write production-grade C++ code and perform detailed code reviews. Guide performance analysis and debugging across the full stackfrom firmware and drivers to user-level runtime libraries. Collaborate with architects, silicon teams, and ML researchers to build future-proof software stacks. Team & Project Management: Mentor and coach junior and senior engineers to grow technical depth and autonomy. Own end-to-end project planning, execution, and delivery, ensuring high-quality output across sprints/releases. Facilitate strong cross-functional communication with hardware, product, and other software teams globally. Recruit and grow a top-tier engineering team in Bangalore, contributing to the hiring strategy and team culture. Required Qualifications: Bachelors or Master’s degree in Computer Science, Electrical Engineering, or related field. 18+ years of experience in systems software development with significant time spent in C++, including architectural and hands-on roles. Proven experience in either: Linux kernel, bootloaders, firmware, or low-level platform software, or Machine Learning compilers (e.g., MLIR, TVM, Glow) or runtimes (e.g., ONNX Runtime, TensorRT, vLLM). Excellent communication skills—written and verbal. Prior experience in project leadership or engineering management with direct reports. Highly Desirable: Understanding of AI/ML compute workloads, particularly Large Language Models (LLMs). Familiarity with performance profiling, bottleneck analysis, and compiler-level optimizations. Exposure to AI accelerators, systolic arrays, or vector SIMD programming. Why Join Us? Work at the forefront of AI systems software, shaping the future of ML compilers and runtimes. Collaborate with globally distributed teams in a fast-paced, innovation-driven environment. Build and lead a technically elite team from the ground up in a growth-stage organization. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"