8.0 - 13.0 years

35 - 65 Lacs

Hyderabad, Pune, Bengaluru

Work from Office

Job Title: STA Full-Chip Lead Location: Bangalore / Hyderabad / Noida / Chennai (Hybrid or On-site) Experience: 8 18 Years Job Type: Full-Time | Permanent Industry: Semiconductor / VLSI / ASIC Design Functional Area: Physical Design / STA / Timing Signoff Job Description We are seeking an experienced and detail-oriented Full-Chip STA Lead to join our high-performance ASIC/SOC design team. You will be responsible for leading full-chip static timing analysis (STA) efforts, driving timing convergence, and managing STA signoff activities across multiple blocks and subsystems. This is a lead-level role requiring deep technical expertise in STA flows and tools, as well as the ability to collaborate with cross-functional teams including RTL, PnR, DFT, and physical verification. Key Responsibilities Own and drive full-chip STA flow , methodology, and signoff. Define and manage SDC constraints for top-level and multi-mode/multi-corner (MMMC) analysis. Perform setup/hold, cross-talk, IR drop-aware timing analysis , and provide ECO guidance for convergence. Collaborate with physical design, RTL, and DFT teams to resolve timing issues across partitions. Work closely with tool/methodology teams to define STA automation, reports, and dashboard mechanisms . Perform signoff-level timing checks : SI, CRPR, path-based analysis, and report generation. Drive STA-related reviews, documentation, and inter-team discussions to meet tapeout timelines. Participate in floorplan feasibility and clock architecture discussions to reduce timing risks early. Support timing correlation between RTL vs. netlist, PnR vs. signoff, and signoff vs. silicon validation. Required Skills & Qualifications B.E/B.Tech or M.E/M.Tech in Electronics/ECE/VLSI or equivalent. 814 years of hands-on STA experience in ASIC/SoC designs, including at least 3 years in a full-chip lead role . Proven track record in closing full-chip STA at advanced nodes (7nm, 5nm, 3nm, or 16FF+). Strong hands-on experience with PrimeTime, Tempus , and industry-standard STA flows. Deep understanding of clock tree structures, multi-mode/multi-corner (MMMC) , and signoff flows. Excellent debugging and scripting skills (Tcl, Perl, Python). Experience with low power design (UPF), hierarchical STA, and ECO timing flows. Exposure to physical design flows and PnR tool interactions (ICC2, Innovus) is highly desirable. Nice to Have: Experience with signoff dashboards and automation frameworks. Familiarity with EMIR-aware timing analysis (RedHawk/Voltus). Experience in STA correlation with post-silicon measurements. Why Join Us? Work on next-generation SoCs in AI, Automotive, Mobile, and Networking domains. Opportunity to lead critical tapeout projects with Tier-1 customers. Fast-track leadership growth with technically challenging and rewarding work. Competitive compensation, training, and certification support.

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